The Zynq BookPDF电子书下载
- 电子书积分:15 积分如何计算积分?
- 作 者:Louise H.Crockett
- 出 版 社:Ist Edition
- 出版年份:2014
- ISBN:0992978709
- 页数:460 页
CHAPTER 1 Introduction 1
1.1 System-on-Chip with Zynq 2
1.2 Simple Anatomy of an Embedded SoC 5
1.3 Design Reuse 7
1.4 Raising the Abstraction Level 7
1.5 SoC Design Flow 8
1.6 Practical Elements 10
1.7 About This Book 10
1.8 References 12
PART A Getting to Know Zynq 13
CHAPTER 2 The Zynq Device (“What is it?”) 15
2.1 Processing System 16
2.1.1 Application Processing Unit (APU) 17
2.1.2 A Note on the ARM Model 20
2.1.3 Processing System External Interfaces 21
2.2 Programmable Logic 22
2.2.1 The Logic Fabric 23
2.2.2 Special Resources:DSP48E1s and Block RAMs 25
2.2.3 General Purpose Input/Output 28
2.2.4 Communications Interfaces 29
2.2.5 Other Programmable Logic External Interfaces 29
2.3 Processing System — Programmable Logic Interfaces 30
2.3.1 The AXI Standard 30
2.3.2 AXI Interconnects and Interfaces 31
2.3.3 EMIO Interfaces 34
2.3.4 Other PL-PS Signals 34
2.4 Security 35
2.4.1 Secure Boot 35
2.4.2 Hardware Support 36
2.4.3 Runtime Security 36
2.5 Zynq-7000 Family Members 39
2.6 Chapter Review 40
2.7 Architecture Reference Guide 41
2.8 References 44
CHAPTER 3 Designing with Zynq (“How do I work with it?”) 47
3.1 Getting Started 48
3.1.1 Obtaining Design Tools 48
3.1.2 Design Tool Editions and Licensing 49
3.1.3 Design Tool Functionality 50
3.1.4 Third Party Tools 51
3.1.5 System Setup and Requirements 51
3.2 An Outline of the Design Flow 53
3.2.1 Requirements and Specification 54
3.2.2 System Design 54
3.2.3 Hardware Development and Testing 55
3.2.4 Software Development and Testing 58
3.2.5 System Integration and Testing 60
3.3 SoC Design Teams 60
3.4 System-Level IP-Focused Design with Vivado 62
3.5 The ISE and Vivado Design Suites 64
3.5.1 Features Comparison 64
3.5.2 Upgrading to Vivado 66
3.6 Development Boards 67
3.6.1 Zynq-7000 SoC ZC702 Evaluation Kit 67
3.6.2 Zynq-7000 SoC Video & Imaging Kit 69
3.6.3 Zynq-7000 ZC706 Evaluation Kit 69
3.6.4 ZedBoard 69
3.6.5 ZYBO 69
3.6.6 Third Party Boards 70
3.6.7 Accessories and Expansions 71
3.6.8 Working with Development Boards 72
3.7 Support and Documentation 72
3.8 Chapter Review 72
3.9 References 73
CHAPTER 4 Device Comparisons (“Why do I need Zynq?”) 77
4.1 Device Selection Criteria 78
4.2 Comparison A:Zynq versus FPGA 80
4.2.1 MicroBlaze Processor 80
4.2.2 MicroBlaze MicroController System 84
4.2.3 PicoBlaze 85
4.2.4 ARM Cortex-M1 85
4.2.5 Other Processor Types 85
4.2.6 Summary Comments 87
4.3 Comparison B:Zynq versus Standard Processor 89
4.3.1 Processor Operation 89
4.3.2 Execution Profiling 92
4.3.3 Summary Comments 94
4.4 Comparison C:Zynq versus a Discrete FPGA-Processor Combination 94
4.5 Exploiting the Zynq Architecture and Design Flow 96
4.6 Chapter Review 98
4.7 References 99
CHAPTER 5 Applications and Opportunities(“What can I do with it?”) 101
5.1 An Overview of Applications 102
5.1.1 Automotive 102
5.1.2 Communications 102
5.1.3 Defence and Aerospace 103
5.1.4 Robotics,Control and Instrumentation 103
5.1.5 Image and Video Processing 104
5.1.6 Medical 105
5.1.7 High Performance Computing (HPC) 105
5.1.8 Others and Future Applications 105
5.2 When Can Zynq Really Help…? 106
5.3 Communications:Software Defined Radio (SDR) 107
5.3.1 Trends in Wireless Communications 107
5.3.2 Introducing Software Defined Radio (SDR) 108
5.3.3 SDR Implementation and Enabling Technologies 108
5.3.4 Cognitive Radio 110
5.4 Smart Systems and Smart Networks 111
5.4.1 What is a Smart System? 111
5.4.2 Examples of Smart Systems 112
5.4.3 Smart Networks:Communications for Smart Systems 114
5.4.4 Related Concepts 115
5.5 Image and Video Processing,and Computer Vision 115
5.5.1 Image and Video Processing 115
5.5.2 Computer Vision 116
5.5.3 Levels of Abstraction 117
5.5.4 Implementation of Image Processing Systems 118
5.5.5 Computer Vision on Zynq Example:Road Sign Recognition 120
5.6 Dynamic System-on-Chip 121
5.6.1 Run Time System Flexibility 121
5.6.2 Dynamic Partial Reconfiguration (DPR) 121
5.6.3 DPR Application Examples 122
5.6.4 Benefits of DPR 124
5.7 Further Opportunities:the Zynq ‘EcoSystem’ 125
5.7.1 What is the Ecosystem? 125
5.7.2 What is the Opportunity? 126
5.8 Chapter Review 128
5.9 References 128
CHAPTER 6 The ZedBoard 133
6.1 Introducing Zed 133
6.2 ZedBoard System Architecture 134
6.3 The Design Flow for ZedBoard 136
6.4 Getting Started with the ZedBoard 137
6.4.1 What’s in the Box? 137
6.4.2 Hardware Setup 137
6.4.3 Programming the ZedBoard 138
6.5 MicroZed 142
6.6 Documentation,Tutorials and Support 142
6.6.1 Documentation about the ZedBoard 142
6.6.2 Demonstrations and Tutorials 143
6.6.3 Online Courseware 143
6.6.4 Other ZedBoard Resources and Support 144
6.7 ZedBoard.org Community 144
6.7.1 Community Projects 144
6.7.2 Blogs 145
6.7.3 Support Forums 145
6.8 Chapter Review 145
6.9 References 146
CHAPTER 7 Education,Research and Training 147
7.1 Technology Trends and SoC Education 148
7.2 University Teaching with Zynq 149
7.2.1 Teaching with Xilinx Tools and Boards 149
7.2.2 Digital Design and FPGA Teaching 150
7.2.3 Computer Science 150
7.2.4 Embedded Systems and SoC Design 150
7.2.5 Algorithm Implementation (e.g.Signal,Image,and Video Processing) 151
7.2.6 Design Reuse 152
7.2.7 New and Emerging Design Methods 153
7.2.8 Sensing,Robotics,and Prototyping 154
7.2.9 An Example Course 154
7.3 Projects and Competitions 155
7.4 Academic Research 156
7.5 The Xilinx University Program (XUP) 158
7.5.1 Introducing XUP 158
7.5.2 Software Support and Licenses 158
7.5.3 XUP Development and Teaching Boards 159
7.5.4 XUP Workshops and Training Materials 159
7.5.5 Technical Support for Universities 160
7.5.6 Eligibility 160
7.5.7 Getting in Touch with XUP 160
7.6 Training for Industry 160
7.6.1 Courses and Authorised Training Providers 160
7.6.2 Other Resources 161
7.6.3 Online Videos 161
7.7 Chapter Review 161
7.8 References 162
CHAPTER 8 First Designs on Zynq 165
8.1 Software Installation Guide 166
8.2 Aims and Outcomes 166
8.3 Overview of Exercise 1A 166
8.4 Overview of Exercise 1 B 167
8.5 Overview of Exercise 1 C 168
8.6 Possible Extensions 169
8.7 What Next? 169
8.8 References 169
PART B Zynq SoC & Hardware Design 171
CHAPTER 9 Embedded Systems and FPGAs 173
9.1 What is an Embedded System? 173
9.1.1 Applications 174
9.1.2 Generic Embedded System Architecture 175
9.2 Processors 176
9.2.1 Co-processors 177
9.2.2 Processor Cache 178
9.2.3 Execution Cycles 180
9.2.4 Interrupts 183
9.3 Buses 184
9.3.1 System and Peripheral Buses 185
9.3.2 Bus Masters and Slaves 186
9.3.3 Bus Arbitration 186
9.3.4 Memory Access 187
9.3.5 Bus Bandwidth 188
9.4 Chapter Review 189
9.5 References 189
CHAPTER 10 Zynq System-on-Chip Design Overview 191
10.1 Interfacing and Signals 192
10.1.1 PS-PL AXI Interfaces 192
10.1.2 PL Co-Processing Interfaces 193
10.1.3 Interrupt Interface 196
10.2 Interconnects 197
10.2.1 Interconnect Features 197
10.2.2 Interconnects,Masters and Slaves 198
10.2.3 Connectivity 199
10.2.4 AXI HP Interfaces 200
10.2.5 AXI ACP Interface 202
10.2.6 AXI GP Interfaces 202
10.3 Memory 202
10.3.1 Memory Interfaces 203
10.3.2 On-Chip Memory (OCM) 208
10.3.3 Memory Map 210
10.4 Interrupts 211
10.4.1 Interrupt Signals 212
10.4.2 Generic Interrupt Controller (GIC) 212
10.4.3 Interrupt Sources 213
10.4.4 Interrupt Prioritisation and Handling 217
10.4.5 Further Reading 218
10.5 Chapter Review 219
10.6 References 219
CHAPTER 11 Zynq System-on-Chip Development 221
11.1 Hardware/Software Partitioning 221
11.2 Profiling 224
11.3 Software Development Tools 226
11.3.1 Software Tools 226
11.3.2 Hardware Configuration Tools 227
11.3.3 Software Development Kit (SDK) 228
11.3.4 Microprocessor Debugger 228
11.3.5 Sourcery CodeBench Lite Edition for Xilinx Cortex-A9 Compiler Toolchain 229
11.3.6 Logic Analysers 229
11.3.7 System Generator for DSP 229
11.4 Chapter Review 230
11.5 References 230
CHAPTER 12 Next Steps in Zynq SoC Design 231
12.1 Prerequisites 231
12.2 Aims and Outcomes 232
12.3 Overview of Exercise 2A 232
12.4 Overview of Exercise 2B 232
12.5 Overview of Exercise 2C 233
12.6 Overview of Exercise 2D 234
12.7 Possible Extensions 235
12.8 What Next? 236
CHAPTER 13 IP Block Design 237
13.1 Overview 237
13.2 Industry Trends and Philosophy 239
13.3 IP Core Design Methods 240
13.3.1 HDL 240
13.3.2 System Generator 241
13.3.3 HDL Coder 241
13.3.4 Vivado High-Level Synthesis 243
13.3.5 Choosing the Right IP Creation Method 244
13.4 Simulation and Documentation 244
13.4.1 Simulation 244
13.4.2 Documentation 249
13.5 Chapter Review 252
13.6 References 252
CHAPTER 14 Spotlight on High-Level Synthesis 255
14.1 High-Level Synthesis Concepts 256
14.1.1 What is High-Level Synthesis (HLS)? 256
14.1.2 Motivations for High-Level Synthesis 257
14.1.3 Design Metrics and Hardware Architectures 259
14.2 Development of HLS Tools 260
14.3 HLS Source Languages 262
14.3.1 C 262
14.3.2 C++ 263
14.3.3 SystemC 263
14.3.4 Other Languages for High-Level Synthesis 264
14.4 Introducing Vivado HLS 264
14.4.1 What Does Vivado HLS Do? 264
14.4.2 Vivado HLS Design Flow 267
14.4.3 C Functional Verification and C/RTL Cosimulation 269
14.4.4 Implementation Metrics and Considerations 271
14.4.5 Overview of the High-Level Synthesis Process 272
14.4.6 Solutions:Exploring the Design Space 276
14.4.7 Vivado HLS Library Support 277
14.5 HLS in the Design Flow for Zynq 277
14.6 Chapter Review 278
14.7 References 278
CHAPTER 15 Vivado HLS:A Closer Look 281
15.1 Anatomy of a Vivado HLS Project 282
15.2 Vivado HLS User Interfaces 283
15.2.1 Graphical User Interface 284
15.2.2 Command Line Interface (CLI) 286
15.3 Data Types 287
15.3.1 C and C++ Native Data Types 287
15.3.2 Vivado HLS Arbitrart Precision Data Types for C and C++ 289
15.3.3 Arbitrary Precision Types for SystemC 292
15.3.4 Floating Point Data Types and Operators 294
15.3.5 Validation of Arbitrary Precision Models 294
15.4 Interface Specification and Synthesis 295
15.4.1 C/C++ Function Definition 295
15.4.2 Synthesis of Port-Level Interfaces 296
15.4.3 Port Interface Protocol Types 298
15.4.4 Synthesis of Port Interface Protocols 300
15.4.5 Block-Level Interface Ports and Protocols 302
15.4.6 Interface Synthesis Directives 304
15.4.7 Manual Interface Specification 308
15.5 Algorithm Synthesis 309
15.5.1 Implementation Metrics and Constraints 309
15.5.2 Data Types 311
15.5.3 Pipelining 311
15.5.4 Dataflow 316
15.5.5 Algorithm Case Study:Loops 319
15.5.6 Arrays 327
15.6 Design Evaluation and Optimisation 328
15.6.1 Design Constraints 328
15.6.2 Synthesis Directives 329
15.6.3 Statistics and Reports 329
15.6.4 Design Iterations and Optimisation 329
15.7 Exporting from Vivado HLS 330
15.7.1 Vivado IP Catalog (IP-XACT Format) 330
15.7.2 System Generator for DSP 330
15.7.3 Pcore for XPS 330
15.8 Chapter Review 331
15.9 References 331
CHAPTER 16 Designing With Vivado High Level Synthesis 333
16.1 Prerequisites 333
16.2 Aims and Outcomes 333
16.3 Overview of Exercise 3A 334
16.4 Overview of Exercise 3B 334
16.5 Overview of Exercise 3C 334
16.6 Possible Extensions 335
16.7 What Next? 335
CHAPTER 17 IP Creation 337
17.1 Aims and Outcomes 337
17.2 Overview of Exercise 4A 338
17.3 Overview of Exercise 4B 338
17.4 Overview of Exercise 4C 339
17.5 Possible Extensions 340
17.6 What Next? 341
CHAPTER 18 IP Reuse and Integration 343
18.1 Overview 343
18.2 System Design — A System-Level Approach 344
18.3 IP-XACT 346
18.4 IP Libraries 346
18.4.1 Vivado IP Catalog 346
18.4.2 Third-Party 347
18.4.3 Custom IP 349
18.5 IP Integration 349
18.5.1 IP Integrator 349
18.5.2 IP Packager 349
18.6 Chapter Review 351
18.7 References 351
CHAPTER 19 AXI Interfacing 353
19.1 Development of AXI 353
19.2 Variations of AXI4 354
19.3 AXI Architecture 354
19.3.1 Address Channels 356
19.3.2 Write Data Channel 356
19.3.3 Read Data Channel 356
19.3.4 Write Response Channel 356
19.4 Examples of Applications 356
19.5 AXI Transactions 358
19.5.1 AXI Write-Burst Transaction 358
19.5.2 AXI Read-Burst Transaction 358
19.6 AXI in the Xilinx Toolflow 360
19.7 Summary 364
19.8 References 364
CHAPTER 20 Adventures with IP Integrator 365
20.1 Aims and Outcomes 366
20.2 Exercise 4A 367
20.3 Exercise 4B 367
20.4 Exercise 4C 368
20.5 Possible Extensions 368
20.6 What Next? 368
PART C Operating Systems & System Integration 369
CHAPTER 21 Introduction to Operating Systems on Zynq 371
21.1 Why Use an Embedded Operating System? 371
21.1.1 Reducing Time to Market 371
21.1.2 Make Use of Existing Features 372
21.1.3 Reduce Maintenance and Development Costs 373
21.2 Choosing the Right Type of Operating System 373
21.2.1 Standalone Operating Systems 374
21.2.2 Real-Time Operating Systems (RTOS) 374
21.2.3 Other Embedded Operating Systems 375
21.2.4 Further Considerations 377
21.3 Applications 377
21.4 Multi-Processor Systems 378
21.5 Zynq Operating Systems 379
21.5.1 Linux 379
21.5.2 RTOS 382
21.5.3 Further Operating Systems 382
21.6 Chapter Review 383
21.7 References 383
CHAPTER 22 Linux:An Overview 385
22.1 A Brief History 385
22.2 Linux System Overview 386
22.3 Licensing 387
22.3.1 GNU General Public licence 388
22.4 Development Tools and Resources 389
22.4.1 Virtual Machines 389
22.4.2 Version Control 391
22.4.3 Git 392
22.4.4 Debugging Linux 393
22.5 Chapter Review 395
22.6 References 396
CHAPTER 23 The Linux Kernel 397
23.1 Linux Kernel Hierarchy 397
23.2 System Call Interface 398
23.3 Memory Management 400
23.3.1 Virtual Memory 400
23.3.2 High and Low Memory 401
23.4 Process Management 401
23.4.1 Process Representation 402
23.4.2 Process Creation,Scheduling and Destruction 402
23.5 File System 404
23.5.1 Linux File Systems 404
23.5.2 Virtual File System 405
23.6 Architecture-Dependent Code 406
23.7 Linux Device Drivers 406
23.7.1 A Note on Mechanisms Vs.Policies 407
23.7.2 Module/Device Classification 407
23.8 Chapter Review 408
23.9 References 408
CHAPTER 24 Linux Booting 409
24.1 Overview 409
24.2 Stages of the Desktop Linux Boot Process 411
24.2.1 BIOS 411
24.2.2 First-Stage Bootloader (FSBL) 411
24.2.3 Second-Stage Bootloader (SSBL) 412
24.2.4 Kernel 413
24.2.5 Init 413
24.3 Booting Zynq 414
24.3.1 Zynq Boot Files 416
24.3.2 Stage-0 (Boot ROM) 417
24.3.3 Stage-1 (First-Stage Bootloader) 419
24.3.4 Stage-2 (Second-Stage Bootloader) 425
24.4 Chapter Review 425
24.5 References 426
Postscript 427
Glossary 429
List of Acronyms 439
Index 451
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