CHAPTER 1 Introduction to Microprocessor Design 1
1.1 Overview of Microprocessor Design 3
1.2 Design Abstraction Levels 6
1.3 Examples of a 2-to-1 Multiplexer 7
1.3.1 Behavioral Level 7
1.3.2 Gate Level 9
1.3.3 Transistor Level 11
1.4 Introduction to Hardware Description Language 11
1.5 Synthesis 15
1.6 Going Forward 16
1.7 Problems 17
CHAPTER 2 Fundamentals of Digital Circuits 18
2.1 Binary Numbers 19
2.1.1 Counting in Binary 20
2.1.2 Converting between Binary and Decimal 20
2.1.3 Octal and Hexadecimal Notations 23
2.1.4 Binary Number Arithmetic 25
2.2 Negative Numbers 27
2.2.1 Two’s Complement Representation 27
2.2.2 Sign Extension 29
2.2.3 Signed Number Arithmetic 30
2.3 Binary Switch 32
2.4 Basic Logic Operators and Logic Expressions 33
2.5 Logic Gates 35
2.6 Truth Tables 36
2.7 Boolean Algebra and Boolean Equations 38
2.7.1 Boolean Algebra 38
2.7.2 Duality Principle 41
2.7.3 Boolean Functions and Their Inverses 41
2.8 Minterms and Maxterms 46
2.8.1 Minterms 46
2.8.2 Maxterms 49
2.9 Canonical,Standard,and Non-Standard Forms 52
2.10 Digital Circuits 53
2.11 Designing a Car Security System 54
2.12 Verilog and VHDL Code for Digital Circuits 57
2.12.1 Verilog Code for a Boolean Function 57
2.12.2 VHDL Code for a Boolean Function 58
2.13 Problems 59
CHAPTER 3 Combinational Circuits 65
3.1 Analysis of Combinational Circuits 66
3.1.1 Using a Truth Table 67
3.1.2 Using a Boolean Function 70
3.2 Synthesis of Combinational Circuits 72
3.2.1 Using Only NAND Gates 75
3.3 Minimization of Combinational Circuits 76
3.3.1 Boolean Algebra 77
3.3.2 Karnaugh Maps 78
3.3.3 Don’t-Cares 85
3.3.4 Tabulation Method 86
3.4 Timing Hazards and Glitches 89
3.4.1 Using Glitches 91
3.5 BCD to 7-Segment Decoder 92
3.6 Verilog and VHDL Code for Combinational Circuits 95
3.6.1 Structural Verilog Code 95
3.6.2 Structural VHDL Code 97
3.6.3 Dataflow Verilog Code 101
3.6.4 Dataflow VHDL Code 102
3.6.5 Behavioral Verilog Code 103
3.6.6 Behavioral VHDL Code 104
3.7 Problems 106
CHAPTER 4 Standard Combinational Components 112
4.1 Signal Naming Conventions 113
4.2 Multiplexer 114
4.3 Adder 117
4.3.1 Full Adder 117
4.3.2 Ripple-Carry Adder 118
4.3.3 Carry-Lookahead Adder 120
4.4 Subtractor 123
4.5 Adder-Subtractor Combination 125
4.6 Arithmetic Logic Unit 129
4.7 Decoder 137
4.8 Tri-State Buffer 140
4.9 Comparator 142
4.10 Shifter 146
4.11 Multiplier 149
4.12 Problems 151
CHAPTER 5 Sequential Circuits 157
5.1 Bistable Element 159
5.2 SR Latch 160
5.3 Car Security System—Version 2 163
5.4 SR Latch with Enable 164
5.5 D Latch 164
5.6 D Latch with Enable 166
5.7 Verilog and VHDL Code for Memory Elements 166
5.7.1 VHDL Code for a D Latch with Enable 168
5.7.2 Verilog Code for a D Latch with Enable 169
5.8 Clock 169
5.9 D Flip-Flop 171
5.9.1 Alternative Smaller Circuit 175
5.10 D Flip-Flop with Enable 176
5.10.1 Asynchronous Inputs 177
5.11 Description of a Flip-Flop 180
5.11.1 Characteristic Table 180
5.11.2 Characteristic Equation 180
5.11.3 State Diagram 180
5.12 Register 181
5.13 Register File 182
5.14 Memories 188
5.14.1 ROM 190
5.14.2 RAM 192
5.15 Shift Registers 197
5.15.1 Serial-to-Parallel Shift Register 199
5.15.2 Serial-to-Parallel and Parallel-to-Serial Shift Register 200
5.15.3 Linear Feedback Shift Register 202
5.16 Counters 205
5.16.1 Binary Up Counter 205
5.16.2 Binary Up Counter with Parallel Load 207
5.17 Timing Issues 210
5.18 Problems 211
CHAPTER 6 Finite-State Machines 215
6.1 Finite-State Machine Models 217
6.2 State Diagrams 221
6.3 Analysis of Finite-State Machines 224
6.3.1 Next-State Equations 225
6.3.2 Next-State Table 226
6.3.3 Output Equations 228
6.3.4 Output Table 228
6.3.5 State Diagram 229
6.3.6 Example 230
6.4 Synthesis of Finite-State Machines 234
6.4.1 State Diagram 235
6.4.2 Next-State Table 236
6.4.3 Next-State Equations 237
6.4.4 Output Table and Output Equations 237
6.4.5 FSM Circuit 238
6.5 Optimizations for FSMs 239
6.5.1 State Reduction 239
6.5.2 State Encoding 240
6.5.3 Unused States 243
6.6 FSM Construction Examples 243
6.6.1 Car Security System—Version 3 243
6.6.2 Modulo-6 UP-Counter 245
6.6.3 One-Shot Circuit 249
6.6.4 Simple Microprocessor Control Unit 251
6.6.5 Elevator Controller Using a Moore FSM 254
6.6.6 Elevator Controller Using a Mealy FSM 258
6.7 Verilog and VHDL Code for FSM Circuits 261
6.7.1 Behavioral Verilog Code for a Moore FSM 261
6.7.2 Behavioral Verilog Code for a Mealy FSM 265
6.7.3 Behavioral VHDL Code for a Moore FSM 266
6.7.4 Behavioral VHDL Code for a Mealy FSM 269
6.8 Problems 270
CHAPTER 7 Dedicated Microprocessors 283
7.1 Need for a Datapath 286
7.2 Constructing the Datapath 287
7.2.1 Selecting Registers 293
7.2.2 Selecting Functional Units 294
7.2.3 Data Transfer Methods 295
7.2.4 Generating Status Signals 297
7.3 Constructing the Control Unit 302
7.3.1 Deriving the Control Signals 303
7.3.2 Deriving the State Diagram 305
7.3.3 Timing Issues 312
7.3.4 Deriving the FSM Circuit 315
7.4 Constructing the Complete Microprocessor 320
7.5 Dedicated Microprocessor Construction Examples 323
7.5.1 Greatest Common Divisor 323
7.5.2 High-Low Number Guessing Game 330
7.5.3 Traffic Light Controller 337
7.6 Verilog and VHDL Code for Dedicated Microprocessors 341
7.6.1 FSM+D Model 342
7.6.2 FSMD Model 351
7.6.3 Algorithmic Model 354
7.7 Problems 356
CHAPTER 8 General-Purpose Microprocessors 362
8.1 Overview of the CPU Design 363
8.2 The EC-1 General-Purpose Microprocessor 365
8.2.1 I nstruction Set 365
8.2.2 Datapath 366
8.2.3 Control Unit 368
8.2.4 Complete Circuit 372
8.2.5 Sample Program 372
8.2.6 Simulation 374
8.2.7 Hardware Implementation 374
8.3 The EC-2 General-Purpose Microprocessor 375
8.3.1 Instruction Set 375
8.3.2 Datapath 376
8.3.3 Control Unit 378
8.3.4 Complete Circuit 383
8.3.5 Sample Program 383
8.3.6 Hardware Implementation 386
8.4 Extending the EC-2 Instruction Set 387
CHAPTER 9 Interfacing Microprocessors 390
9.1 Multiplexing 7-Segment LED Display 391
9.1.1 Theory of Operation 391
9.1.2 Controller Design 392
9.2 Issues with Interfacing Switches 393
9.3 3×4 Keypad Controller 401
9.3.1 Theory of Operation 401
9.3.2 Controller Design 404