Preface 1
Chapter 1 Introduction to Protel 7
1.1 First Coming into Protel 7
1.1.1 Development 7
1.1.2 Windows of Protel 8
1.1.3 Composing of Protel 8
1.1.4 Machine Hardware Demand for Protel 10
1.1.5 Documents in Protel 11
1.2 Environment Setting 12
1.2.1 Protel Servers 12
1.2.2 System Preferences 13
1.2.3 Design Teams 14
Chapter 2 Schematic Design in Protel 17
2.1 Process of Simple Schematic Design 17
2.1.1 Settings for Schematic Design 18
2.1.2 Preparing Components 20
2.1.3 Place and Align Component 26
2.1.4 Annotation the schematic 31
2.1.5 Schematic Design Verification—the ERC 33
2.1.6 Generating a Schematic Netlist 35
2.2 Design of Complex Schematic 39
2.2.1 Introduction 39
2.2.2 Hierarchical Methods for Complex Design 39
2.2.3 ERC on a Multi-Sheet 42
2.3 Create or Edit Our Own Schematic Component 48
2.3.1 Introduction to Library Editor 48
2.3.2 Create Our Own Component Library 50
2.3.3 Properties of Component 52
Chapter 3 PCB Design in Protel 55
3.1 Foreword of PCB 55
3.1.1 Have a Knowledge of PCB 55
3.1.2 Operating on PCB 56
3.2 Process of PCB Design 57
3.2.1 The Interface Between Schematic and PCB 58
3.2.2 Working Environment Settings 59
3.2.3 PCB Design Objects 62
3.2.4 Load Netlist 66
3.2.5 Positioning PCB Components 74
3.2.6 PCB Design Rules 79
3.2.7 Autorouting a PCB 81
3.2.8 PCB Design Rule Checker(DRC) 85
3.3 PCB Footprint Libraries 87
3.3.1 PCB Libraries 87
3.3.2 Footprint Making 89
3.4 Recommend Some Protel Methods for Product Design 93
Chapter 4 Simulations in Protel 95
4.1 Introduction of Schematic Simulation 95
4.1.1 Introduction of Simulation 95
4.1.2 Components for Simulation 96
4.1.3 Setting up for Simulation Displaying 108
4.2 Stimulation by Protel 109
4.2.1 Stimulation by Protel 109
4.2.2 Waveform Analysis Viewer 121
4.2.3 Examples for Stimulation 122
4.2.4 Checking the Signal Integrity of a PCB 126
Chapter 5 Simple Introduction to PowerLogic and PowerPCB 133
5.1 Introduction 133
5.1.1 New Functionality in Powers 133
5.1.2 The Powers of Windows 135
5.1.3 Document Management in Powers 136
5.1.4 Hot key in Powers 137
5.1.5 Design Flow Chart in Powers 142
5.2 Design in Powers 143
5.2.1 Settings 143
5.2.2 Component Libraries 148
5.2.3 Schematic Design 153
5.2.4 Communication between Powers 155
5.2.5 PCB Design 158
5.3 Loading Netlist from Protel 99 in PowerPCB 167
Chapter 6 Introduction to FPGA 168
6.1 Summary of Hardware Description Language 168
6.1.1 Brief Introduction 168
6.1.2 Basic Program Structure of VHDL 169
6.2 VHDL Fundament 172
6.2.1 Definition of VHDL Data 172
6.2.2 VHDL Arithmetic Operators 176
6.3 VHDL Statements 179
6.3.1 Summing up VHDL Statements 179
6.3.2 Parallel VHDL 179
6.3.3 Sequential VHDL 184
6.4 Design Improvement 194
6.4.1 Combinational Logic Circuit 194
6.4.2 Sequential Logic Circuit 202
6.5 Quartus Ⅱ Software Development 208
6.5.1 Brief Introduction to the Software 208
6.5.2 Design Flow 209
6.5.3 Creating a Project 209
6.5.4 Design Entry 213
6.5.5 Compilation 219
6.5.6 Simulation 221
6.5.7 Configure/Program 226
参考文献 230