1 Introduction to Analog Design 1
1.1 Why Analog？ 1
1.2 Why Integrated？ 6
1.3 Why CMOS？ 6
1.4 Why This Book？ 7
1.5 General Concepts 7
1.5.1 Levels of Abstraction 7
1.5.2 Robust Analog Design 7
2 Basic MOS Device Physics 9
2.1 General Considerations 10
2.1.1 MOSFET as a Switch 10
2.1.2 MOSFET Structure 10
2.1.3 MOS Symbols 12
2.2 MOS I/V Characteristics 13
2.2.1 Threshold Voltage 13
2.2.2 Derivation of I/V Characteristics 15
2.3 Second-Order Effects 23
2.4 MOS Device Models 28
2.4.1 MOS Device Layout 28
2.4.2 MOS Device Capacitances 29
2.4.3 MOS Small-Signal Model 33
2.4.4 MOS SPICE models 36
2.4.5 NMOS versus PMOS Devices 37
2.4.6 Long-Channel versus Short-Channel Devices 38
3 Single-Stage Amplifiers 47
3.1 Basic Concepts 47
3.2 Common-Source Stage 48
3.2.1 Common-Source Stage with Resistive Load 48
3.2.2 CS Stage with Diode-Connected Load 53
3.2.3 CS Stage with Current-Source Load 58
3.2.4 CS Stage with Triode Load 59
3.2.5 CS Stage with Source Degeneration 60
3.3 Source Follower 67
3.4 Common-Gate Stage 76
3.5 Cascode Stage 83
3.5.1 Folded Cascode 90
3.6 Choice of Device Models 92
4 Differential Amplifiers 100
4.1 Single-Ended and Differential Operation 100
4.2 Basic Differential Pair 103
4.2.1 Qualitative Analysis 104
4.2.2 Quantitative Analysis 107
4.3 Common-Mode Response 118
4.4 Differential Pair with MOS Loads 124
4.5 Gilbert Cell 126
5 Passive and Active Current Mirrors 135
5.1 Basic Current Mirrors 135
5.2 Cascode Current Mirrors 139
5.3 Active Current Mirrors 145
5.3.1 Large-Signal Analysis 149
5.3.2 Small-Signal Analysis 151
5.3.3 Common-Mode Properties 154
6 Frequency Response of Amplifiers 166
6.1 General Considerations 166
6.1.1 Miller Effect 166
6.1.2 Association of Poles with Nodes 169
6.2 Common-Source Stage 172
6.3 Source Followers 178
6.4 Common-Gate Stage 183
6.5 Cascode Stage 185
6.6 Differential Pair 187
Appendix A：Dual of Miller’s Theorem 193
7 Noise 201
7.1 Statistical Characteristics of Noise 201
7.1.1 Noise Spectrum 203
7.1.2 Amplitude Distribution 206
7.1.3 Correlated and Uncorrelated Sources 207
7.2 Types of Noise 209
7.2.1 Thermal Noise 209
7.2.2 Flicker Noise 215
7.3 Representation of Noise in Circuits 218
7.4 Noise in Single-Stage Amplifiers 224
7.4.1 Common-Source Stage 225
7.4.2 Common-Gate Stage 228
7.4.3 Source Followers 231
7.4.4 Cascode Stage 232
7.5 Noise in Differential Pairs 233
7.6 Noise Bandwidth 239
8 Feedback 246
8.1 General Considerations 246
8.1.1 Properties of Feedback Circuits 247
8.1.2 Types of Amplifiers 254
8.2 Feedback Topologies 258
8.2.1 Voltage-Voltage Feedback 258
8.2.2 Current-Voltage Feedback 263
8.2.3 Voltage-Current Feedback 266
8.2.4 Current-Current Feedback 269
8.3 Effect of Loading 270
8.3.1 Two-Port Network Models 270
8.3.2 Loading in Voltage-Voltage Feedback 272
8.3.3 Loading in Current-Voltage Feedback 275
8.3.4 Loading in Voltage-Current Feedback 278
8.3.5 Loading in Current-Current Feedback 281
8.3.6 Summary of Loading Effects 283
8.4 Effect of Feedback on Noise 284
9 Operational Amplifiers 291
9.1 General Considerations 291
9.1.1 Performance Parameters 291
9.2 One-Stage Op Amps 296
9.3 Two-Stage Op Amps 307
9.4 Gain Boosting 309
9.5 Comparison 313
9.6 Common-Mode Feedback 314
9.7 Input Range Limitations 325
9.8 Slew Rate 326
9.9 Power Supply Rejection 334
9.10 Noise in Op Amps 336
10 Stability and Frequency Compensation 345
10.1 General Considerations 345
10.2 Multipole Systems 349
10.3 Phase Margin 351
10.4 Frequency Compensation 355
10.5 Compensation of Two-Stage Op Amps 361
10.5.1 Slewing in Two-Stage Op Amps 368
10.6 Other Compensation Techniques 369
11 Bandgap References 377
11.1 General Considerations 377
11.2 Supply-Independent Biasing 377
11.3 Temperature-Independent References 381
11.3.1 Negative-TC Voltage 381
11.3.2 Positive-TC Voltage 382
11.3.3 Bandgap Reference 384
11.4 PTAT Current Generation 390
11.5 Constant-Gm Biasing 392
11.6 Speed and Noise Issues 393
11.7 Case Study 397
12 Introduction to Switched-Capacitor Circuits 405
12.1 General Considerations 405
12.2 Sampling Switches 410
12.2.1 MOSFETS as Switches 410
12.2.2 Speed Considerations 414
12.2.3 Precision Considerations 417
12.2.4 Charge Injection Cancellation 421
12.3 Switched-Capacitor Amplifiers 423
12.3.1 Unity-Gain Sampler/Buffer 424
12.3.2 Noninverting Amplifier 432
12.3.3 Precision Multiply-by-Two Circuit 438
12.4 Switched-Capacitor Integrator 439
12.5 Switched-Capacitor Common-Mode Feedback 442
13 Nonlinearity and Mismatch 448
13.1 Nonlinearity 448
13.1.1 General Considerations 448
13.1.2 Nonlinearity of Differential Circuits 452
13.1.3 Effect of Negative Feedback on Nonlinearity 454
13.1.4 Capacitor Nonlinearity 457
13.1.5 Linearization Techniques 458
13.2 Mismatch 463
13.2.1 Offset Cancellation Techniques 471
13.2.2 Reduction of Noise by Offset Cancellation 476
13.2.3 Alternative Definition of CMRR 478
14 Oscillators 482
14.1 General Considerations 482
14.2 Ring Oscillators 484
14.3 LC Oscillators 495
14.3.1 Crossed-Coupled Oscillator 499
14.3.2 Colpitts Oscillator 502
14.3.3 One-Port Oscillators 505
14.4 Voltage-Controlled Oscillators 510
14.4.1 Tuning in Ring Oscillators 512
14.4.2 Tuning in LC Oscillators 521
14.5 Mathematical Model of VCOs 525
15 Phase-Locked Loops 532
15.1 Simple PLL 532
15.1.1 Phase Detector 532
15.1.2 Basic PLL Topology 533
15.1.3 Dynamics of Simple PLL 542
15.2 Charge-Pump PLLs 549
15.2.1 Problem of Lock Acquisition 549
15.2.2 Phase/Frequency Detector and Charge Pump 550
15.2.3 Basic Charge-Pump PLL 556
15.3 Nonideal Effects in PLLs 562
15.3.1 PFD/CP Nonidealities 562
15.3.2 Jitter in PLLs 567
15.4 Delay-Locked Loops 569
15.5 Applications 572
15.5.1 Frequency Multiplication and Synthesis 572
15.5.2 Skew Reduction 574
15.5.3 Jitter Reduction 576
Appendix A Short-Channel Effects and Device Models 579
A.1 Scaling Theory 579
A.2 Short-Channel Effects 583
A.2.1 Threshold Voltage Variation 583
A.2.2 Mobility Degradation with Vertical Field 585
A.2.3 Velocity Saturation 587
A.2.4 Hot Carrier Effects 589
A.2.5 Output Impedance Variation with Drain-Source Voltage 589
A.3 MOS Device Models 591
A.3.1 Level 1 Model 592
A.3.2 Level 2 Model 593
A.3.3 Level 3 Model 595
A.3.4 BSM Series 596
A.3.5 Other Models 597
A.3.6 Charge and Capacitance Modeling 598
A.3.7 Temperature Dependence 599
A.4 Process Corners 599
A.5 Analog Design in a Digital World 600
Appendix B CMOS Processing Technology 604
B.1 General Considerations 604
B.2 Wafer Processing 605
B.3 Photolithography 606
B.4 Oxidation 608
B.5 Ion Implantation 608
B.6 Deposition and Etching 611
B.7 Device Fabrication 611
B.7.1 Active Devices 611
B.7.2 Passive Devices 616
B.7.3 Interconnects 624
B.8 Latch-Up 627
Appendix C Layout and Packaging 631
C.1 General Layout Considerations 631
C.1.1 Design Rules 632
C.1.2 Antenna Effect 634
C.2 Analog Layout Techniques 635
C.2.1 Multifinger Transistors 635
C.2.2 Symmetry 637
C.2.3 Reference Distribution 642
C.2.4 Passive Devices 644
C.2.5 Interconnects 653
C.3 Substrate Coupling 660
Index 677