Chapter 1 From Zero to One 3
1.1 The Game Plan 3
1.2 The Art of Managing Complexity 4
1.2.1 Abstraction 4
1.2.2 Discipline 5
1.2.3 The Three-Y's 6
1.3 The Digital Abstraction 7
1.4 Number Systems 9
1.4.1 Decimal Numbers 9
1.4.2 Binary Numbers 9
1.4.3 Hexadecimal Numbers 11
1.4.4 Bytes,Nibbles,and All That Jazz 13
1.4.5 Binary Addition 14
1.4.6 Signed Binary Numbers 15
1.5 Logic Gates 19
1.5.1 NOT Gate 20
1.5.2 Buffer 20
1.5.3 AND Gate 20
1.5.4 OR Gate 21
1.5.5 Other Two-Input Gates 21
1.5.6 Multiple-Input Gates 21
1.6 Beneath the Digital Abstraction 22
1.6.1 Supply Voltage 22
1.6.2 Logic Levels 22
1.6.3 Noise Margins 23
1.6.4 DC Transfer Characteristics 23
1.6.5 The Static Discipline 24
1.7 CMOS Transistors 26
1.7.1 Semiconductors 27
1.7.2 Diodes 27
1.7.3 Capacitors 28
1.7.4 nMOS and pMOS Transistors 28
1.7.5 CMOS NOT Gate 31
1.7.6 Other CMOS Logic Gates 31
1.7.7 Transmission Gates 33
1.7.8 Pseudo-nMOS Logic 33
1.8 Power Consumption 34
1.9 Summary and a Look Ahead 35
Exercises 37
Interview Questions 48
Chapter 2 Combinational Logic Design 51
2.1+ Introduction 51
2.2 Boolean Equations 54
2.2.1 Terminology 54
2.2.2 Sum-of-Products Form 54
2.2.3 Product-of-Sums Form 56
2.3 Boolean Algebra 56
2.3.1 Axioms 57
2.3.2 Theorems of One Variable 57
2.3.3 Theorems of Several Variables 58
2.3.4 The Truth Behind It All 60
2.3.5 Simplifying Equations 61
2.4 From Logic to Gates 62
2.5 Multilevel Combinational Logic 65
2.5.1 Hardware Reduction 66
2.5.2 Bubble Pushing 67
2.6 X's and Z's,Oh My 69
2.6.1 Illegal Value：X 69
2.6.2 Floating Value：Z 70
2.7 Karnaugh Maps 71
2.7.1 Circular Thinking 73
2.7.2 Logic Minimization with K-Maps 73
2.7.3 Don't Cares 77
2.7.4 The Big Picture 78
2.8 Combinational Building Blocks 79
2.8.1 Multiplexers 79
2.8.2 Decoders 82
2.9 Timing 84
2.9.1 Propagation and Contamination Delay 84
2.9.2 Glitches 88
2.10 Summary 91
Exercises 93
Interview Questions 100
Chapter 3 Sequential Logic Design 103
3.1 Introduction 103
3.2 Latches and Flip-Flops 103
3.2.1 SR Latch 105
3.2.2 D Latch 107
3.2.3 D Flip-Flop 108
3.2.4 Register 108
3.2.5 Enabled Flip-Flop 109
3.2.6 Resettable Flip-Flop 110
3.2.7 Transistor-Level Latch and Flip-Flop Designs 110
3.2.8 Putting It All Together 112
3.3 Synchronous Logic Design 113
3.3.1 Some Problematic Circuits 113
3.3.2 Synchronous Sequential Circuits 114
3.3.3 Synchronous and Asynchronous Circuits 116
3.4 Finite State Machines 117
3.4.1 FSM Design Example 117
3.4.2 State Encodings 123
3.4.3 Moore and Mealy Machines 126
3.4.4 Factoring State Machines 129
3.4.5 FSM Review 132
3.5 Timing of Sequential Logic 133
3.5.1 The Dynamic Discipline 134
3.5.2 System Timing 135
3.5.3 Clock Skew 140
3.5.4 Metastability 143
3.5.5 Synchronizers 144
3.5.6 Derivation of Resolution Time 146
3.6 Parallelism 149
3.7 Summary 153
Exercises 155
Interview Questions 165
Chapter 4 Hardware Description Languages 167
4.1 Introduction 167
4.1.1 Modules 167
4.1.2 Language Origins 168
4.1.3 Simulation and Synthesis 169
4.2 Combinational Logic 171
4.2.1 Bitwise Operators 171
4.2.2 Comments and White Space 174
4.2.3 Reduction Operators 174
4.2.4 Conditional Assignment 175
4.2.5 Internal Variables 176
4.2.6 Precedence 178
4.2.7 Numbers 179
4.2.8 Z's and X's 179
4.2.9 Bit Swizzling 182
4.2.10 Delays 182
4.2.11 VHDL Libraries and Types 183
4.3 Structural Modeling 185
4.4 Sequential Logic 190
4.4.1 Registers 190
4.4.2 Resettable Registers 191
4.4.3 Enabled Registers 193
4.4.4 Multiple Registers 194
4.4.5 Latches 195
4.5 More Combinational Logic 195
4.5.1 Case Statements 198
4.5.2 If Statements 199
4.5.3 Verilog casez 201
4.5.4 Blocking and Nonblocking Assignments 201
4.6 Finite State Machines 206
4.7 Parameterized Modules 211
4.8 Testbenches 214
4.9 Summary 218
Exercises 219
Interview Questions 230
Chapter 5 Digital Building Blocks 233
5.1 Introduction 233
5.2 Arithmetic Circuits 233
5.2.1 Addition 233
5.2.2 Subtraction 240
5.2.3 Comparators 240
5.2.4 ALU 242
5.2.5 Shifters and Rotators 244
5.2.6 Multiplication 246
5.2.7 Division 247
5.2.8 Further Reading 248
5.3 Number Systems 249
5.3.1 Fixed-Point Number Systems 249
5.3.2 Floating-Point Number Systems 250
5.4 Sequential Building Blocks 254
5.4.1 Counters 254
5.4.2 Shift Registers 255
5.5 Memory Arrays 257
5.5.1 Overview 257
5.5.2 Dynamic Random Access Memory 260
5.5.3 Static Random Access Memory 260
5.5.4 Area and Delay 261
5.5.5 Register Files 261
5.5.6 Read Only Memory 262
5.5.7 Logic Using Memory Arrays 264
5.5.8 Memory HDL 264
5.6 Logic Arrays 266
5.6.1 Programmable Logic Array 266
5.6.2 Field Programmable Gate Array 268
5.6.3 Array Implementations 273
5.7 Summary 274
Exercises 276
Interview Questions 286
Chapter 6 Architecture 289
6.1 Introduction 289
6.2 Assembly Language 290
6.2.1 Instructions 290
6.2.2 Operands：Registers,Memory,and Constants 292
6.3 Machine Language 299
6.3.1 R-type Instructions 299
6.3.2 I-type Instructions 301
6.3.3 J-type Instructions 302
6.3.4 Interpreting Machine Language Code 302
6.3.5 The Power of The Stored Program 303
6.4 Programming 304
6.4.1 Arithmetic/Logical Instructions 304
6.4.2 Branching 308
6.4.3 Conditional Statements 310
6.4.4 Getting Loopy 311
6.4.5 Arrays 314
6.4.6 Procedure Calls 319
6.5 Addressing Modes 327
6.6 Lights,Camera,Action：Compiling,Assembling,and Loading 330
6.6.1 The Memory Map 330
6.6.2 Translating and Starting a Program 331
6.7 Odds and Ends 336
6.7.1+ Pseudoinstructions 336
6.7.2 Exceptions 337
6.7.3 Signed and Unsigned Instructions 338
6.7.4 Floating-Point Instructions 340
6.8 Real-World Perspective：IA-32 Architecture 341
6.8.1 M-32 Registers 342
6.8.2 M-32 Operands 342
6.8.3 Status Flags 344
6.8.4 IA-32 Instructions 344
6.8.5 M-32 Instruction Encoding 346
6.8.6 Other IA-32 Peculiarities 348
6.8.7 The Big Picture 349
6.9 Summary 349
Exercises 351
Interview Questions 361
Chapter 7 Microarchitecture 363
7.1 Introduction 363
7.1.1 Architectural State and Instruction Set 363
7.1.2 Design Process 364
7.1.3 MIPS Microarchitectures 366
7.2 Performance Analysis 366
7.3 Single-Cycle Processor 368
7.3.1 Single-Cycle Datapath 368
7.3.2 Single-Cycle Control 374
7.3.3+ More Instructions 377
7.3.4 Performance Analysis 380
7.4 Multicycle Processor 381
7.4.1 Multicycle Datapath 382
7.4.2 Multicycle Control 388
7.4.3 More Instructions 395
7.4.4 Performance Analysis 397
7.5 Pipelined Processor 401
7.5.1 Pipelined Datapath 404
7.5.2 Pipelined Control 405
7.5.3 Hazards 406
7.5.4 More Instructions 418
7.5.5 Performance Analysis 418
7.6 HDL Representation 421
7.6.1 Single-Cycle Processor 422
7.6.2 Generic Building Blocks 426
7.6.3 Testbench 428
7.7 Exceptions 431
7.8 Advanced Microarchitecture 435
7.8.1 Deep Pipelines 435
7.8.2 Branch Predicuon 437
7.8.3 Superscalar Processor 438
7.8.4 Out-of-Order Processor 441
7.8.5 Register Renaming 443
7.8.6 Single Instruction Multiple Data 445
7.8.7 Multithreading 446
7.8.8 Multiprocessors 447
7.9 Real-World Perspective：IA-32 Microarchitecture 447
7.10 Summary 453
Exercises 455
Interview Questions 461
Chapter 8 Memory Systems 463
8.1 Introduction 463
8.2 Memory System Performance Analysis 467
8.3 Caches 468
8.3.1 What Data Is Held in the Cache? 469
8.3.2 How Is the Data Found? 470
8.3.3 What Data Is Replaced? 478
8.3.4 Advanced Cache Design 479
8.3.5 The Evolution of MIPS Caches 483
8.4 Virtual Memory 484
8.4.1 Address Translation 486
8.4.2 The Page Table 488
8.4.3 The Translation Lookaside Buffer 490
8.4.4 Memory Protection 491
8.4.5 Replacement Policies 492
8.4.6 Multilevel Page Tables 492
8.5 Memory-Mapped I/O 494
8.6 Real-World Perspective：IA-32 Memory and I/O Systems 499
8.6.1 IA-32 Cache Systems 499
8.6.2 M-32 Virtual Memory 501
8.6.3 IA-32 Programmed I/O 502
8.7 Summary 502
Exercises 504
Interview Questions 512
Appendix A Digital System Implementation 515
A.1 Introduction 515
A.2 74xx Logic 515
A.2.1 Logic Gares 516
A.2.2 Other Functions 516
A.3 Programmable Logic 516
A.3.1 PROMs 516
A.3.2 PLAs 520
A.3.3 FPGAs 521
A.4 Application-Specific Integrated Circuits 523
A.5 Data Sheets 523
A.6 Logic Families 529
A.7 Packaging and Assembly 531
A.8 Transmission lines 534
A.8.1 Matched Termination 536
A.8.2 Open Termination 538
A.8.3 Short Termination 539
A.8.4 Mismatched Termination 539
A.8.5 When to Use Transmission Line Models 542
A.8.6 Proper Transmission Line Terminations 542
A.8.7 Derivation of Z0 544
A.8.8 Derivation of the Reflection Coefficient 545
A.8.9 Putting It All Together 546
A.9 Economics 547
Appendix B MIPS Instructions 551
Further Reading 555
Index 557