Chapter 1 Welcome to VLSI 1
1.1 A Brief History 1
1.2 Preview 6
1.3 MOS Transistors 6
1.4 CMOS Logic 9
1.4.1 The Inverter 9
1.4.2 The NAND Gate 9
1.4.3 CMOS Logic Gates 9
1.4.4 The NOR Gate 11
1.4.5 Compound Gates 11
1.4.6 Pass Transistors and Transmission Gates 12
1.4.7 Tristates 14
1.4.8 Multiplexers 15
1.4.9 Sequential Circuits 16
1.5 CMOS Fabrication and Layout 19
1.5.1 Inverter Cross-Section 19
1.5.2 Fabrication Process 20
1.5.3 Layout Design Rules 24
1.5.4 Gate Layouts 27
1.5.5 Stick Diagrams 28
1.6 Design Partitioning 29
1.6.1 Design Abstractions 30
1.6.2 Structured Design 31
1.6.3 Behavioral,Structural,and Physical Domains 31
1.7 Example:A Sinple MIPS Microprocessor 33
1.7.1 MIPS Architecture 33
1.7.2 Multicycle MIPS Microarchitecture 34
1.8 Logic Design 38
1.8.1 Top-Level Interfaces 38
1.8.2 Block Diagrams 38
1.8.3 Hierarchy 40
1.8.4 Hardware Description Languages 40
1.9 Circuit Design 42
1.10 Physical Design 45
1.10.1 Floorplanning 45
1.10.2 Standard Cells 48
1.10.3 Pitch Matching 50
1.10.4 Slice Plans 50
1.10.5 Arrays 51
1.10.6 Area Estimation 51
1.11 Design Veri.cation 53
1.12 Fabrication,Packaging,and Testing 54
Summary and a Look Ahead 55
Exercises 57
Chapter 2 Devices 61
2.1 Introduction 61
2.2 Long-Channel I-V Characteristics 64
2.3 C-V Characteristics 68
2.3.1 Simple MOS Capacitance Models 68
2.3.2 Detailed MOS Gate Capacitance Model 70
2.3.3 Detailed MOS Diffusion Capacitance Model 72
2.4 Nonideal I-V Effects 74
2.4.1 Mobility Degradation and Velocity Saturation 75
2.4.2 Channel Length Modulation 78
2.4.3 Threshold Voltage Effects 79
2.4.4 Leakage 80
2.4.5 Temperature Dependence 85
2.4.6 Geometry Dependence 86
2.4.7 Summary 86
2.5 DC Transfer Characteristics 87
2.5.1 Static CMOS Inverter DC Characteristics 88
2.5.2 Beta Ratio Effects 90
2.5.3 Noise Margin 91
2.5.4 Pass Transistor DC Characteristics 92
2.6 Pitfalls and Fallacies 93
Summary 94
Exercises 95
Chapter 3 Speed 99
3.1 Introduction 99
3.1.1 De.nitions 99
3.1.2 Timing Optimization 100
3.2 Transient Response 101
3.3 RC Delay Model 104
3.3.1 Effective Resistance 104
3.3.2 Gate and Diffusion Capacitance 105
3.3.3 Equivalent RC Circuits 105
3.3.4 Transient Response 106
3.3.5 Elmore Delay 108
3.3.6 Layout Dependence of Capacitance 111
3.3.7 Determining Effective Resistance 112
3.4 Linear Delay Model 113
3.4.1 Logical Effort 114
3.4.2 Parasitic Delay 114
3.4.3 Delay in a Logic Gate 116
3.4.4 Drive 117
3.4.5 Extracting Logical Effort from Datasheets 117
3.4.6 Limitations to the Linear Delay Model 118
3.5 Logical Effort of Paths 121
3.5.1 Delay in Multistage Logic Networks 121
3.5.2 Choosing the Best Number of Stages 124
3.5.3 Example 126
3.5.4 Summary and Observations 127
3.5.5 Limitations of Logical Effort 129
3.5.6 Iterative Solutions for Sizing 129
3.6 Timing Analysis Delay Models 131
3.6.1 Slope-Based Linear Model 131
3.6.2 Nonlinear Delay Model 132
3.6.3 Current Source Model 132
3.7 Pitfalls and Fallacies 132
3.8 Historical Perspectives 133
Summary 134
Exercises 134
Chapter 4 Power 139
4.1 Introduction 139
4.1.1 De.nitions 140
4.1.2 Examples 140
4.1.3 Sources of Power Dissipation 142
4.2 Dynamic Power 143
4.2.1 Activity Factor 144
4.2.2 Capacitance 146
4.2.3 Voltage 148
4.2.4 Frequency 150
4.2.5 Short-Circuit Current 151
4.2.6 Resonant Circuits 151
4.3 Static Power 152
4.3.1 Static Power Sources 152
4.3.2 Power Gating 155
4.3.3 Multiple Threshold Voltages and Oxide Thicknesses 157
4.3.4 Variable Threshold Voltages 157
4.3.5 Input Vector Control 158
4.4 Energy-Delay Optimization 158
4.4.1 Minimum Energy 158
4.4.2 Minimum Energy-Delay Product 161
4.4.3 Minimum Energy Under a Delay Constraint 161
4.5 Low Power Architectures 162
4.5.1 Microarchitecture 162
4.5.2 Parallelism and Pipelining 162
4.5.3 Power Management Modes 163
4.6 Pitfalls and Fallacies 164
4.7 Historical Perspective 165
Summary 167
Exercises 167
Chapter 5 Wires 169
5.1 Introduction 169
5.1.1 Wire Geometry 169
5.1.2 Example:Intel Metal Stacks 170
5.2 Interconnect Modeling 171
5.2.1 Resistance 172
5.2.2 Capacitance 173
5.2.3 Inductance 176
5.2.4 Skin Effect 177
5.2.5 Temperature Dependence 178
5.3 Interconnect Impact 178
5.3.1 Delay 178
5.3.2 Energy 180
5.3.3 Crosstalk 180
5.3.4 Inductive Effects 182
5.3.5 An Aside on Effective Resistance and Elmore Delay 185
5.4 Interconnect Engineering 187
5.4.1 Width,Spacing,and Layer 187
5.4.2 Repeaters 188
5.4.3 Crosstalk Control 190
5.4.4 Low-Swing Signaling 192
5.4.5 Regenerators 194
5.5 Logical Effort with Wires 194
5.6 Pitfalls and Fallacies 195
Summary 196
Exercises 196
Chapter 6 Scaling,Reliability,and Variability 199
6.1 Introduction 199
6.2 Variability 199
6.2.1 Supply Voltage 200
6.2.2 Temperature 200
6.2.3 Process Variation 201
6.2.4 Design Corners 202
6.3 Reliability 204
6.3.1 Reliability Terminology 204
6.3.2 Oxide Wearout 205
6.3.3 Interconnect Wearout 207
6.3.4 Soft Errors 209
6.3.5 Overvoltage Failure 210
6.3.6 Latchup 211
6.4 Scaling 212
6.4.1 Transistor Scaling 213
6.4.2 Interconnect Scaling 215
6.4.3 International Technology Roadmap for Semiconductors 216
6.4.4 Impacts on Design 217
6.5 Statistical Analysis of Variability 221
6.5.1 Properties of Random Variables 221
6.5.2 Variation Sources 224
6.5.3 Variation Impacts 227
6.6 Variation-Tolerant Design 232
6.6.1 Adaptive Control 233
6.6.2 Fault Tolerance 233
6.7 Pitfalls and Fallacies 235
6.8 Historical Perspective 236
Summary 242
Exercises 242
Chapter 7 SPICE 245
7.1 Introduction 245
7.2 A SPICE Tutorial 246
7.2.1 Sources and Passive Components 246
7.2.2 Transistor DC Analysis 250
7.2.3 Inverter Transient Analysis 250
7.2.4 Subcircuits and Measurement 252
7.2.5 Optimization 254
7.2.6 Other HSPICE Commands 256
7.3 Device Models 256
7.3.1 Level 1 Models 257
7.3.2 Level 2 and 3 Models 258
7.3.3 BSIM Models 258
7.3.4 Diffusion Capacitance Models 258
7.3.5 Design Comers 260
7.4 Device Characterization 261
7.4.1 I-V Characteristics 261
7.4.2 Threshold Voltage 264
7.4.3 Gate Capacitance 266
7.4.4 Parasitic Capacitance 266
7.4.5 Effective Resistance 268
7.4.6 Comparison of Processes 269
7.4.7 Process and Environmental Sensitivity 271
7.5 Circuit Characterization 271
7.5.1 Path Simulations 271
7.5.2 DC Transfer Characteristics 273
7.5.3 Logical Effort 273
7.5.4 Power and Energy 276
7.5.5 Simulating Mismatches 277
7.5.6 Monte Carlo Simulation 277
7.6 Interconnect Simulation 277
7.7 Pitfalls and Fallacies 280
Summary 282
Exercises 282
Chapter 8 Gates 285
8.1 Introduction 285
8.2 Circuit Families 286
8.2.1 Static CMOS 287
8.2.2 Ratioed Circuits 292
8.2.3 Cascode Voltage Switch Logic 297
8.2.4 Dynamic Circuits 297
8.2.5 Pass-Transistor Circuits 307
8.3 Circuit Pitfalls 312
8.3.1 Threshold Drops 313
8.3.2 Ratio Failures 313
8.3.3 Leak age 314
8.3.4 Charge Sharing 314
8.3.5 Power Supply Noise 314
8.3.6 Hot Spots 315
8.3.7 Minority Carrier Injection 315
8.3.8 Back-Gate Coupling 316
8.3.9 Diffusion Input Noise Sensitivity 316
8.3.10 Process Sensitivity 316
8.3.11 Example:Domino Noise Budgets 317
8.4 Silicon-On-Insulator Circuit Design 318
8.4.1 Floating Body Voltage 319
8.4.2 SOI Advantages 320
8.4.3 SOI Disadvantages 320
8.4.4 Implications for Circuit Styles 321
8.4.5 Summary 322
8.5 Subthreshold Circuit Design 322
8.5.1 Sizing 323
8.5.2 Gate Selection 323
8.6 Pitfalls and Fallacies 324
8.7 Historical Perspective 325
Summary 327
Exercises 328
Chapter 9 Sequencing 333
9.1 Introduction 333
9.2 Sequencing Static Circuits 334
9.2.1 Sequencing Methods 334
9.2.2 Max-Delay Constraints 337
9.2.3 Min-Delay Constraints 341
9.2.4 Time Borrowing 344
9.2.5 Clock Skew 347
9.3 Circuit Design of Latches and Flip-Flops 349
9.3.1 Conventional CMOS Latches 350
9.3.2 Conventional CMOS Flip-Flops 351
9.3.3 Pulsed Latches 353
9.3.4 Resettable Latches and Flip-Flops 354
9.3.5 Enabled Latches and Flip-Flops 355
9.3.6 Incorporating Logic into Latches 356
9.3.7 Klass Semidynamic Flip-Flop(SDFF) 357
9.3.8 Differential Flip-Flops 357
9.3.9 Dual Edge-Triggered Flip-Flops 358
9.3.10 Radiation-Hardened Flip-Flops 359
9.4 Static Sequencing Element Methodology 360
9.4.1 Choice of Elements 361
9.4.2 Characterizing Sequencing Element Delays 363
9.4.3 State Retention Registers 366
9.4.4 Level-Converter Flip-Flops 366
9.4.5 Design Margin and Adaptive Sequential Elements 367
9.5 Synchronizers 369
9.5.1 Metastability 370
9.5.2 A Simple Synchronizer 373
9.5.3 Communicating Between Asynchronous Clock Domains 374
9.5.4 Common Synchronizer Mistakes 375
9.5.5 Arbiters 377
9.5.6 Degrees of Synchrony 377
9.6 Wave Pipelining 378
9.7 Pitfalls and Fallacies 380
Summary 381
Exercises 383
Chapter 10 Datapaths 387
10.1 Introduction 387
10.2 Addition/Subtraction 387
10.2.1 Single-Bit Addition 388
10.2.2 Carry-Propagate Addition 392
10.2.3 Subtraction 416
10.2.4 Multiple-Input Addition 416
10.2.5 Flagged Prefix Adders 417
10.3 One/Zero Detectors 419
10.4 Comparators 420
10.4.1 Magnitude Comparator 420
10.4.2 Equality Comparator 420
10.4.3 K＝A+B Comparator 421
10.5 Counters 421
10.5.1 Binary Counters 422
10.5.2 Fast Binary Counters 423
10.5.3 Ring and Johnson Counters 424
10.5.4 Linear-Feedback Shift Registers 424
10.6 Boolean Logical Operations 426
10.7 Coding 426
10.7.1 Parity 426
10.7.2 Error-Correcting Codes 426
10.7.3 Gray Codes 428
10.7.4 XOR/XNOR Circuit Forms 429
10.8 Shifters 430
10.8.1 Funnel S hifter 431
10.8.2 Barrel Shifter 433
10.8.3 Alternative Shift Functions 434
10.9 Multiplication 434
10.9.1 Unsigned Array Multiplication 436
10.9.2 Two's Complement Array Multiplication 437
10.9.3 Booth Encoding 438
10.9.4 Column Addition 443
10.9.5 Final Addition 447
10.9.6 Fused Multiply-Add 448
10.9.7 Summary 448
10.10 Parallel-Prefix Computations 449
10.11 Pitfalls and Fallacies 451
Summary 452
Exercises 452
Chapter 11 Memories 455
11.1 Introduction 455
11.2 SRAM 456
11.2.1 SRAM Cells 457
11.2.2 Row Circuitry 464
11.2.3 Column Circuitry 468
11.2.4 Multi-Ported SRAM and Register Files 472
11.2.5 Large SRAMs 473
11.2.6 Low-Power SRAMs 475
11.2.7 Area,Delay,and Power of RAMs and Register Files 478
11.3 DRAM 480
11.3.1 Subarray Architectures 481
11.3.2 Column Circuitry 483
11.3.3 Embedded DRAM 484
11.4 Read-Only Memory 485
11.4.1 Programmable ROMs 487
11.4.2 NAND ROMs 488
11.4.3 Flash 489
11.5 Serial Access Memories 491
11.5.1 Shift Registers 491
11.5.2 Queues(FIFO,LIFO) 491
11.6 Content-Addressable Memory 493
11.7 Programmable Logic Arrays 495
11.8 Robust Memory Design 499
11.8.1 Redundancy 499
11.8.2 Error Correcting Codes(ECC) 501
11.8.3 Radiation Hardening 501
11.9 Historical Perspective 501
Summary 503
Exercises 504
Chapter 12 Packaging,Power,Clock,I/O 507
12.1 Introduction 507
12.2 Packaging and Cooling 507
12.2.1 Package Options 507
12.2.2 Chip-to-Package Connections 509
12.2.3 Package Parasitics 510
12.2.4 Heat Dissipation 510
12.2.5 Temperature Sensors 511
12.3 Power Distribution 513
12.3.1 On-Chip Power Distribution Network 514
12.3.2 IR Drops 515
12.3.3 L di/dt Noise 516
12.3.4 On-Chip Bypass Capacitance 517
12.3.5 Power Network Modeling 518
12.3.6 Power Supply Filtering 522
12.3.7 Charge Pumps 522
12.3.8 Substrate Noise 523
12.3.9 Energy Scavenging 523
12.4 Clocks 524
12.4.1 De.nitions 524
12.4.2 Clock System Architecture 526
12.4.3 Global Clock Generation 527
12.4.4 Global Clock Distribution 529
12.4.5 Local Clock Gaters 533
12.4.6 Clock Skew Budgets 535
12.4.7 Adaptive Deskewing 537
12.5 PLLs and DLLs 538
12.5.1 PLLs 538
12.5.2 DLLs 545
12.5.3 Pitfalls 547
12.6 I/O 548
12.6.1 Basic I/O Pad Circuits 549
12.6.2 Electrostatic Discharge Protection 551
12.6.3 Example:MOSIS I/O Pads 552
12.6.4 Mixed-Voltage I/O 554
12.7 High-Speed Links 555
12.7.1 High-Speed I/O Channels 555
12.7.2 Channel Noise and Interference 558
12.7.3 High-Speed Transmitters and Receivers 559
12.7.4 Synchronous Data Transmission 564
12.7.5 Clock Recovery in Source-Synchronous Systems 564
12.7.6 Clock Recovery in Mesochronous Systems 566
12.7.7 Clock Recovery in Pleisochronous Systems 568
12.8 Random Circuits 568
12.8.1 True Random Number Generators 568
12.8.2 Chip Identification 569
12.9 Pitfalls and Fallacies 570
Summary 571
Exercises 572
Chapter 13 Methodology 573
13.1 Introduction 573
13.2 Structured Design Strategies 575
13.2.1 A Software Radio—A System Example 576
13.2.2 Hierarchy 578
13.2.3 Regularity 581
13.2.4 Modularity 583
13.2.5 Locality 584
13.2.6 Summary 585
13.3 Design Methods 585
13.3.1 Microprocessor/DSP 585
13.3.2 Programmable Logic 586
13.3.3 Gate Arrayand Sea of Gates Design 589
13.3.4 Cell-Based Design 590
13.3.5 Full Custom Design 592
13.3.6 Platform-Based Design—System on a ChiP 593
13.3.7 Summary 594
13.4 Design Flows 594
13.4.1 Behavioral Synthesis Design Flow(ASIC Design Flow) 595
13.4.2 Automated Layout Generation 599
13.4.3 Mixed-Signal or Custom-Design Flow 603
13.5 Design Economics 604
13.5.1 Non-Recurring Engineering Costs(NREs) 605
13.5.2 Recurring Costs 607
13.5.3 Fixed Costs 608
13.5.4 Schedule 609
13.5.5 Personpower 611
13.5.6 Project Management 611
13.5.7 Design Reuse 612
13.6 Data Sheets and Documentation 613
13.6.1 The Summary 613
13.6.2 Pinout 613
13.6.3 Description of Operation 613
13.6.4 DC Specifications 613
13.6.5 AC Specifications 614
13.6.6 Package Diagram 614
13.6.7 Principles of Operation Manual 614
13.6.8 User Manual 614
13.7 Pitfalls and Fallacies 615
Exercises 615
Chapter 14 Test 617
14.1 Introduction 617
14.1.1 Logic Veri.cation 618
14.1.2 Debugging 620
14.1.3 Manufacturing Tests 622
14.2 Testers,Test Fixtures,and Test Programs 624
14.2.1 Testers and Test Fixtures 624
14.2.2 Test Programs 626
14.2.3 Handlers 627
14.3 Logic Verification Principles 628
14.3.1 Test Vectors 628
14.3.2 Testbenches and Harnesses 629
14.3.3 Regression Testing 629
14.3.4 Version Control 630
14.3.5 Bug Tracking 631
14.4 Silicon Debug Principles 631
14.5 Manufacturing Test Principles 634
14.5.1 Fault Models 635
14.5.2 Observability 637
14.5.3 Controllability 637
14.5.4 Repeatability 637
14.5.5 Survivability 637
14.5.6 Fault Coverage 638
14.5.7 Automatic Test Pattern Generation(ATPG) 638
14.5.8 Delay Fault Testing 638
14.6 Design for Testability 639
14.6.1 Ad Hoc Testing 639
14.6.2 Scan Design 640
14.6.3 Built-In Self-Test(BIST) 642
14.6.4 IDDQ Testing 645
14.6.5 Design for Manufacturability 645
14.7 Boundary Scan 646
14.8 Testing in a University Environment 647
14.9 Pitfalls and Fallacies 648
Summary 655
Exercises 655
Chapter 15 Fabrication 657
15.1 Introduction 657
15.2 CMOS Technologies 658
15.2.1 Wafer Formation 658
15.2.2 Photolimography 659
15.2.3 Well and Channel Formation 661
15.2.4 Silicon Dioxide(SiO2) 663
15.2.5 Isolation 664
15.2.6 Gate Oxide 665
15.2.7 Gate and Source/Drain Formations 666
15.2.8 Contacts and Metallization 668
15.2.9 Passivation 670
15.2.10 Metrology 670
15.3 Layout Design Rules 671
15.3.1 Design Rule Background 671
15.3.2 Scribe Line and Other Stnctures 674
15.3.3 MOSIS Scalable CMOS Design Rules 675
15.3.4 Micron Design Rules 676
15.4 CMOS Process Enhancements 677
15.4.1 Transistors 677
15.4.2 Interconnect 680
15.4.3 Circuit Elements 682
15.4.4 Beyond Conventional CMOS 687
15.5 Technology-Related CAD Issues 688
15.5.1 Design Rule Checking(DRC) 689
15.5.2 Circuit Extraction 690
15.6 Manufacturing Issues 691
15.6.1 Antenna Rules 691
15.6.2 LayerDensitv Rules 692
15.6.3 Resolution Enhancement Rules 692
15.6.4 Metal Slotting Rules 693
15.6.5 Yield Enhancement Guidelines 693
15.7 Pitfalls and Fallacies 694
15.8 Historical Perspective 695
Summary 697
Exercises 697
References 699
Index 731
Credits 751