数字逻辑设计 VHDL 基础 英文版PDF电子书下载

Chapter 1 DESIGN CONCEPTS 1 1

1．1 Digital Hardware 2

1．1．1 Standard Chips 4

1．1．2 Programmable Logic Devices 4

1．1．3 Custom-Designed Chips 5

1．2 The Design Process 6

1．3 Design of Digital Hardware 8

1．3．1 Basic Design Loop 8

1．3．2 Design of a Digital Hardware Unit 9

1．4 Logic Circuit Design in this Book 12

1．5 Theory and Practice 14

References 15

Chapter 2 INTRODUCTION TO LOGIC CIRCUITS 17

2．1 Variables and Functions 18

2．2 Inversion 21

2．3 Truth Tables 22

2．4 Logic Gates and Networks 23

2．4．1 Analysis of a Logic Network 24

2．5 Boolean Algebra 27

2．5．1 The Venn Diagram 30

2．5．2 Notation and Terminology 34

2．5．3 Precedence of Operations 34

2．6 Synthesis Using AND，OR，and NOT Gates 35

2．6．1 Sum-of-Products and Product-of-Sums Forms 37

2．7 Design Examples 41

2．7．1 Three Way Light Control 42

2．7．2 Multiplexer Circuit 43

2．8 Introduction to CAD Tools 45

2．8．1 Design Entry 46

2．8．2 Synthesis 48

2．8．3 Functional Simulation 49

2．8．4 Summary 49

2．9 Introduction to VHDL 51

2．9．2 Writing Simple VHDL Code 52

4．2 Strategy for Minimization 52

2．9．1 Representation of Digital Signals in VHDL 52

2．9．3 How Not to Write VHDL Code 54

2．10 Concluding Remarks 55

Problems 56

References 60

Chapter 3 IMPLEMENTATION TECHNOLOGY 61

3．1 Transistor Switches 63

3．2 NMOS Logic Gates 65

3．3 CMOS Logic Gates 68

3．3．1 Speed of Logic Gate Circuits 75

3．4 Negative Logic System 76

3．5 Standard Chips 77

3．5．1 7400-Series Standard Chips 77

3．6 Programmable Logic Devices 81

3．6．1 Programmable Logic Array(PLA) 81

3．6．2 Programmable Array Logic(PAL) 84

3．6．3 Programming of PLAs and PALs 86

3．6．4 Complex Programmable Logic Devices (CPLDs) 88

3．6．5 Field-Programmable Gate Arrays 92

3．6．6 Using CAD Tools to Implement Circuits in CPLDs and FPGAs 96

3．7 Custom Chips，Standard Cells，and Gate Arrays 97

3．8 Practical Aspects 100

3．8．1 MOSFET Fabrication and Behavior 100

3．8．2 MOSFET On-Resistance 104

3．8．3 Voltage Levels in Logic Gates 105

3．8．4 Noise Margin 107

3．8．5 Dynamic Operation of Logic Gates 108

3．8．6 Power Dissipation in Logic Gates 111

3．8．7 Passing Is and Os Through Transistor Switches 112

3．8．8 Fan-in and Fan-out in Logic Gates 114

3．9 Transmission Gates 120

3．9．1 Exclusive-OR Gates 121

3．9．2 Multiplexer Circuit 122

3．10 Implementation Details for SPLDs，CPLDs，and FPGAs 123

3．10．1 Implementation in FPGAs 129

3．11 Concluding Remarks 131

Problems 132

References 141

Chapter 4 OPTIMIZED IMPLEMENTATION OF LOGIC FUNCTIONS 143

4．1 Karnaugh Map 144

4．2．1 Terminology 153

4．2．2 Minimization Procedure 154

4．3 Minimization of Product-of-Sums Forms 158

4．4 Incompletely Specified Functions 160

4．5 Multiple-Output Circuits 161

4．6 NAND and NOR Logic Networks 165

4．7 Multilevel Synthesis 167

4．7．1 Factoring 168

4．7．2 Functional Decomposition 171

4．7．3 Multilevel NAND and NOR Circuits 177

4．8 Analysis of Multilevel Circuits 180

4．9 Cubical Representation 185

4．9．1 Cubes and Hypercubes 185

4．10 Minimization Using Cubical Representation 189

4．10．1 Generation of Prime Implicants 189

4．10．2 Determination of Essential Prime Implicants 192

4．10．3 Complete Procedure for Finding a Minimal Cover 194

4．11 Practical Considerations 196

4．12 CAD Tools 197

4．12．1 Logic Synthesis and Optimization 198

4．12．2 Physical Design 199

4．12．3 Timing Simulation 201

4．12．4 Summary of Design Flow 202

4．12．5 Examples of Circuits Synthesized from VHDL Code 204

4．13 Concluding Remarks 210

Problems 211

References 214

Chapter 5 NUMBER REPRESENTATION AND ARITHMETIC CIRCUITS 217

5．1 Positional Number Representation 218

5．1．1 Unsigned Integers 218

5．1．2 Conversion between Decimal and Binary Systems 219

5．1．3 Octal and Hexadecimal Representations 220

5．2 Addition of Unsigned Numbers 222

5．2．1 Decomposed Full-Adder 226

5．2．2 Ripple-Carry Adder 227

5．2．3 Design Example 228

5．3 Signed Numbers 228

5．3．1 Negative Numbers 228

5．3．2 Addition and Subtraction 232

5．3．3 Adder and Subtractor Unit 236

5．3．4 Radix-Complement Schemes 237

5．3．5 Arithmetic Overflow 241

5．3．6 Performance Issues 242

5．4．1 Carrv-Lookahead Adder 243

5．4 Fast Adders 243

5．5 Design of Arithmetic Circuits Using CAD Tools 250

5．5．1 Design of Arithmetic Circuits Using Schematic Capture 250

5．5．2 Design of Arithmetic Circuits Using VHDL 253

5．5．3 Representation of Numbers in VHDL Code 256

5．5．4 Arithmetic Assignment Statements 258

5．6 Multiplication 262

5．6．1 Array Multiplier for Unsigned Numbers 263

5．6．2 Multiplication of Signed Numbers 264

5．7 Other Number Representations 267

5．7．1 Fixed-Point Numbers 267

5．7．2 Floating-Point Numbers 267

5．7．3 Binary-Coded-Decimal Representation 269

5．8 ASCII Character Code 273

Problems 276

References 280

Chapter 6 COMBINATIONAL-CIRCUIT BUILDING BLOCKS 281

6．1 Multiplexers 282

6．1．1 Synthesis of Logic Functions Using Multiplexers 287

6．1．2 Multiplexer Synthesis Using Shannon s Expansion 288

6．2 Decoders 295

6．2．1 Demultiplexers 298

6．3 Encoders 300

6．3．1 Binary Encoders 300

6．3．2 Priority Encoders 301

6．4 Code Converters 302

6．5 Arithmetic Comparison Circuits 304

6．6 VHDL for Combinational Circuits 304

6．6．1 Assignment Statements 305

6．6．2 Selected Signal Assignment 305

6．6．3 Conditional Signal Assignment 308

6．6．4 Generate Statements 312

6．6．5 Concurrent and Sequential Assignment Statements 315

6．6．6 Process Statement 315

6．6．7 Case Statement 321

6．7 Concluding Remarks 324

Problems 326

References 330

Chapter 7 FLIP-FLOPS，REGISTERS，COUNTERS，AND A SIMPLE PROCESSOR 331

7．1 Basic Latch 333

7．2 Gated SR Latch 335

7．2．1 Gated SR Latch with NAND Gates 337

7．3 Gated D Latch 338

7．3．1 Effects of Propagation Delays 340

7．4 Master-Slave and Edge-Triggered D Flip-Flops 341

7．4．1 Master-Slave D Flip-Flop 341

7．4．2 Edge-Triggered D Flip-Flop 342

7．4．3 D FLIP-Flops with Clear and Preset 344

7．5 T Flip-Flop 346

7．5．1 Configurable Flip-Flops 349

7．6 JK Flip-Flop 349

7．8 Registers 350

7．7 Summary of Terminology 350

7．8．1 Shift Register 351

7．8．2 Parallel-Access Shift Register 352

7．9 Counters 353

7．9．1 Asynchronous Counters 353

7．9．2 Synchronous Counters 356

7．9．3 Counters with Parallel Load 360

7．10 Reset Synchronization 360

7．11 Other Types of Counters 364

7．11．1 BCD Counter 364

7．11．2 Ring Counter 365

7．11．3 Johnson Counter 366

7．12 Using Storage Elements with CAD Tools 367

7．12．1 Including Storage Elements in Schematics 367

7．11．4 Remarks on Counter Design 367

7．12．2 Using Latches and Flip-Flops in VHDL Code 370

7．12．3 Using VHDL Sequential Statements for Storage Elements 370

7．13 Using Registers and Counters with CAD Tools 375

7．13．1 Including Registers and Counters in Schematics 375

7．13．2 Registers and Counters in VHDL Code 378

7．13．3 Using VHDL Sequential Statements for Registers and Counters 379

7．14 Design Examples 387

7．14．1 Bus Structure 387

7．14．2 Simple Processor 400

7．14．3 Reaction Timer 413

7．15 Concluding Remarks 418

Problems 418

References 424

Chapter 8 SYNCHRONOUS SEQUENTIAL CIRCUITS 427

8．1 Basic Design Steps 429

8．1．1 State Diagram 429

8．1．2 State Table 431

8．1．3 State Assignment 431

8．1．4 Choice of Flip-Flops and Derivation of Next-State and Output Expressions 433

8．1．5 Timing Diagram 435

8．1．6 Summary of Design Steps 436

8．2 State-Assignment Problem 440

8．2．1 One-Hot Encoding 442

8．3 Mealy State Model 444

8．4 Design of Finite State Machines Using CAD Tools 449

8．4．1 VHDL Code for Moore-Type FSMs 449

8．4．2 Synthesis of VHDL Code 451

8．4．3 Simulating and Testing the Circuit 454

8．4．4 An Alternative Style of VHDL Code 456

8．4．5 Summary of Design Steps When Using CAD Tools 456

8．4．6 Specifying the State Assignment in VHDL Code 458

8．4．7 Specification of Mealy FSMs Using VHDL 459

8．5 Serial Adder Example 463

8．5．1 Mealy-Type FSM for Serial Adder 463

8．5．2 Moore-Type FSM for Serial Adder 464

8．5．3 VHDL Code for the Serial Adder 467

8．6 State Minimization 470

8．6．1 Partitioning Minimization Procedure 473

8．6．2 Incompletely Specified FSMs 480

8．7．2 State Assignment 482

8．7 Design of a Counter Using the Sequential Circuit Approach 482

8．7．1 State Diagram and State Table for a Modulo-8 Counter 482

8．7．3 Implementation Using D-Type Flip-Flops 484

8．7．4 Implementation Using JK-Type Flip-Flops 485

8．7．5 Example-A Different Counter 489

8．8 FSM as an Arbiter Circuit 492

8．8．1 Implementation of the Arbiter Circuit 496

8．8．2 Minimizing the Output Delays for an Fsm 499

8．8．3 Summary 499

8．9 Analysis of Synchronous Sequential Circuits 500

8．10 Algorithmic State Machine(ASM)Charts 504

8．11 Formal Model for Sequential Circuits 507

Problems 509

8．12 Concluding Remarks 509

References 513

Chapter 9 ASYNCHRONOUS SEQUENTIAL CIRCUITS 515

9．1 Asynchronous Behavior 516

9．2 Analysis of Asynchronous Circuits 519

9．3 Synthesis of Asynchronous Circuits 528

9．4 State Reduction 540

9．5 State Assignment 555

9．5．1 Transition Diagram 558

9．5．2 Exploiting Unspecified Next-State Entries 561

9．5．3 State Assignment Using Additional State Variables 565

9．5．4 One-Hot State Assignment 569

9．6 Hazards 571

9．6．1 Static Hazards 572

9．6．2 Dynamic Hazards 576

9．6．3 Significance of Hazards 578

9．7 A Complete Design Example 579

9．7．1 The Vending-Machine Controller 579

9．8 Concluding Remarks 583

Problems 585

References 590

Chapter 10 DIGITAL SYSTEM DESIGN 591

10．1 Building Block Circuits 592

10．1．1 Flip-Flops and Registers with Enable Inputs 592

10．1．2 Shift Registers with Enable Inputs 593

10．1．3 Static Random Access Memory (SRAM) 595

10．2 Design Examples 600

10．2．1 A Bit-Counting Circuit 600

10．1．4 SRAM Blocks in PLDs 600

10．2．2 ASM Chart Implied Timing Information 601

10．2．3 Shift-and-Add Multiplier 603

10．2．4 Divider 612

10．2．5 Arithmetic Mean 623

10．2．6 Sort Operation 629

10．3 Clock Synchronization 639

10．3．1 Clock Skew 640

10．3．2 Filp-Flop Timing Parameters 641

10．3．3 Asynchronous Inputs to Flip-Flops 644

10．4 Concluding Remarks 645

10．3．4 Switch Debouncing 645

Problems 647

References 651

Chapter 11 TESTING OF LOGIC CIRCUITS 653

11．1 Fault Model 654

11．1．1 Stuck-at Model 654

11．1．2 Single and Multiple Faults 655

11．1．3 CMOS Circuits 655

11．2 Complexity of a Test Set 655

11．3 Path Sensitizing 657

11．3．1 Detection of a Specific Fault 659

11．4 Circuits with Tree Structure 661

11．5 Random Tests 662

11．6 Testing of Sequential Circuits 665

11．6．1 Design for Testability 665

11．7 Built-in Self-Test 669

11．7．1 Built-in Logic Block Observer 673

11．7．2 Signature Analysis 675

11．7．3 Boundary Scan 676

11．8 Printed Circuit Boards 676

11．8．1 Testing of PCBs 678

11．8．2 Instrumentation 679

11．9 Concluding Remarks 680

Problems 680

References 683

Appendix A VHDL REFERENCE 685

A．1 Documentation in VHDL Code 686

A．2 Data Objects 687

A．2．1 Data Object Names 687

A．2．2 Data Object Values and Numbers 687

A．2．3 SIGNAL Data Objects 687

A．2．4 BIT and BIT_VECTOR Types 688

A．2．5 STD_LOGIC and STD_LOGIC_VECTOR Types 688

A．2．6 STD_ULOGIC Type 689

A．2．7 SIGNED and UNSIGNED Types 690

A．2．8 INTEGER Type 690

A．2．9 BOOLEAN Type 691

A．2．10 ENUMERATION Type 691

A．2．12 VARIABLE Data Ojbects 692

A．2．13 Type Conversion 692

A．2．11 CONSTANT Data Objects 692

A．2．14 Arrays 693

A．3 Operators 693

A．4 VHDL Design Entity 694

A．4．1 ENTITY Declaration 695

A．4．2 ARCHITECTURE 695

A．5 Package 697

A．6 Using Subcircuits 698

A．6．1 Declaring a COMPONENT in a Package 700

A．7 Concurrent Assignment Statements 701

A．7．1 Simple Signal Assignment 701

A．7．2 Assigning Signal Values Using OTHERS 703

A．7．4 Conditional Signal Assignment 704

A．7．3 Selected Signal Assignment 704

A．7．5 GENERATE Statement 705

A．8 Defining an Entity with GENERICs 707

A．9 Sequential Assignment Statements 707

A．9．1 PROCESS Statement 708

A．9．2 IF Statement 708

A．9．3 CASE Statement 709

A．9．4 LOOP Statements 710

A．9．5 Using a Process for a Combinational Circuit 710

A．9．6 Statement Ordering 711

A．9．7 Using a VARIABLE in a PRocess 712

A．10 Sequential Circuits 716

A．10．2 D Flip-Flop 717

A．10．1 A Gated D Latch 717

A．10．3 Using a WAIT UNTIL Statement 719

A．10．4 A Flip-Flop with Asynchronous Reset 719

A．10．5 Synchronous Reset 719

A．10．6 Instantiating a Flip-Flop from a Library 721

A．10．7 Registers 721

A．10．8 Shift Registers 723

A．10．9 Counters 725

A．10．10 Using Subcircuits with GENERIC Parameters 725

A．10．11 A Moore-Type Finite State Machine 728

A．10．12 A Mealy-Type Finite State Machine 731

A．10．13 Manual State Assignment for a Finite State Machine 731

A．11 Common Errors in VHDL Code 734

References 738

A．12 Concluding Remarks 738

Appendix B TUTORIAL 1 739

B．1 Introduction 740

B．1．1 Getting Started 740

B．2 Design Entry Using Schematic Capture 743

B．2．1 Specifying the Project Name 744

B．2．2 Using the Graphic Editor 744

B．2．3 Synthesizing a Circuit from the Schematic 750

B．2．4 Performing Functional Simulation 751

B．2．5 Using the Message Processor to Locate and Fix Errors 755

B．3 Design Entry Using VHDL 757

B．3．1 Specifying the Project Name 757

B．3．2 Using the Text Editor 757

B．3．4 Performing Functional Simulation 759

B．3．3 Synthesizing a Circuit from the VHDL Code 759

B．3．5 Using the Message Processor to Debug VHDL Code 760

B．4 Design Entry Using Truth Tables 760

B．4．1 Using the Waveform Dditor 760

B．4．2 Create the Timing Diagram 761

B．4．3 Synthesizing a Circuit from the Waveforms 763

B．5 Mixing Design-Entry Methods 764

B．5．1 Creating a Schematic that Includes a Truth Table 764

B．5．2 Synthesizing and Simulating a Circuit from the Schematic 765

B．5．3 Using the Hierarchy Display 766

B．5．4 Concluding Remarks 767

Appendix C TUTORIAL 2 769

C．1 Implementing a Circuit in a MAX 7000 CPLD 770

C．1．1 Using the Compiler 771

C．1．2 Selecting a Chip 772

C．1．3 Viewing the Logic Synthesis Options 773

C．1．4 Examining the Implemented Circuit 774

C．1．5 Running the Timing Simulator 775

C．1．6 Using the Floorplan Editor 776

C．2 Implementing a Circuit in a FLEX 10K FPGA 779

C．3 Downloading a Circuit into a Device 781

C．4 Making Pin Assignments 783

C．4．1 Assigning Signals to Pins in the Floorplan Editor 785

C．4．2 Making Pin Assignments Permanent 786

C．5 Concluding Remarks 787

Appendix D TUTORIAL 3 789

D．1．2 The Ripple-Carry Adder Dode 790

D．1 Design Using Hierarchical VHDL Code 790

D．1．1 The Full-Adder Subcircuit 790

D．1．3 Alternative Style of Code for the Ripple-Carry Adder 795

D．1．4 Using the Timing Analyzer Module 795

D．2 Using an LPM Module 796

D．3 Design of a Sequential Circuit 800

D．3．1 Using the Graphic Editor 800

D．3．2 Synthesizing a Circuit and Using the Timing Simulator 806

D．3．3 Using the Timing Analyzer 807

D．3．4 Using VHDL Code 807

D．4 Design of a Finite State Machine 809

D．4．1 Implementation in a CPLD 810

D．4．2 Implementation in an FPGA 813

D．5 Concluding Remarks 815

Appendix E COMMERCIAL DEVICES 817

E．1 Simple PLDs 818

E．1．1 The 22V10PAL Device 818

E．2 Complex PLDs 820

E．2．1 Altera MAX 7000 821

E．3 Field-Programmable Gate Arrays 822

E．3．1 Altera FLEX 10K 823

E．3．2 Xilinx XC4000 826

E．4 Transistor-Transistor Logic 827

E．4．1 TTL Circuit Families 829

References 830

INDEX 831