The ASIC HandbookPDF电子书下载

Chapter 1 Phases of an ASIC Project 1

1.1 Introduction 1

1.2 List of Phases 1

1.3 Prestudy Phase 3

1.4 Top-Level Design Phase 5

1.5 Module Specification Phase 8

1.5.1 Tasks for the Bulk of the Team 9

1.5.2 Other Tasks 10

1.6 Module Design 11

1.6.1 Tasks for the Bulk of the Team 12

1.6.2 Other Tasks 13

Preface 15

CONTENTS 15

1.7 Subsystem Simulation 15

1.7.1 Tasks for the Subsystem Simulation Team 16

1.7.2 Project Leader Tasks 17

1.8 System Simulation/Synthesis 17

1.8.1 Tasks for the System Simulation Team 18

Acknowledgments 19

1.8.2 Tasks for the Synthesis Team 21

1.8.3 Project Leader Tasks 22

1.9 Layout and the Backend Phase 23

1.10 Postlayout Simulation/Synthesis 25

1.11 ASIC Sign-Off 27

1.12 Preparation for Testing Silicon 28

1.13 Testing of Silicon 30

1.13.1 Project Leader Tasks 32

1.14 Summary 33

Chapter 2 Design Reuse and System-on-a-Chip Designs 35

2.1 Introduction 35

2.2 Reuse Documentation 36

2.2.1 Functional Overview 36

2.2.2 Interface Description 36

2.2.3 Implementation Details 37

2.2.4 Timing Diagrams 37

2.2.5 Test Methodology 37

2.2.6 Clocking Strategy 37

2.2.10 Programmer's Reference Guide 38

2.2.9 Module Validation Approach 38

2.2.7 Source Code Control Strategy 38

2.2.8 Synthesis/Layout Approach 38

2.3 Tips and Guidelines for Reuse 39

2.3.1 Company Standards 39

2.3.2 Coding Style 39

2.3.3 Generics and Constants 40

2.3.4 Clock Domains,Synchronous Design,Registers and Latches 41

2.3.5 Use of Standard Internal Buses 42

2.3.6 CPU-Addressable Registers 42

2.3.8 Verification,Testbenches and Debugging 43

2.3.7 Technology Specifics 43

2.3.9 VHDL versus Verilog 44

2.3.10 Live Documentation 44

2.3.11 Reviewing 44

2.4 SoC and Third-Party IP Integration 44

2.4.1 Developing In-House versus Sourcing Externally 45

2.4.2 Where to Source IP 46

2.4.3 Reducing the Risk with Parallel Third-Party IP Development 47

2.4.4 Issues with Third-Party IP 48

2.4.5 Processor and DSP Cores 50

2.5 System-Level Design Languages 51

2.6 Virtual Socket Interface Alliance 51

2.7 Summary 51

Chapter 3 A Quality Design Approach 53

3.1 Introduction 53

3.2.1 Specifications 54

3.2.2 Hierarchy Diagram 54

3.2 Project Design Documentation 54

3.2.3 Design Route Document 55

3.2.4 Module Documentation 56

3.2.5 The Test Approach Document 56

3.3 Reviews 57

3.3.1 Review of the Architecture Specification/Register Specifications 58

3.4 Module Design and Reviewing 58

3.4.1 Module Specification 58

3.4.2 Module Design Phase 60

3.4.3 Module Coding Phase 62

3.4.4 Module Simulation/Synthesis Phase 63

3.6 Review Checklists 64

3.6.1 Specification Review Checklist 64

3.5 Quality System Simulations 64

3.6.2 Design Documentation Review Checklist 65

3.6.3 Coding Phase Review Checklist 65

3.7 Summary 66

4.1 Introduction 69

4.2 General Coding Guidelines 69

Chapter 4 Tips and Guidelines 69

4.2.1 Simplicity 70

4.2.2 User-Defined Types and Complex Data Types 70

4.2.3 Naming Conventions 71

4.2.4 Constants 72

4.2.5 Use of Comments 72

4.2.6 Indentation 73

4.2.7 Ordering I/O Signals and Variable Declarations 74

4.2.8 Consistent Logic Assertion Levels 74

4.2.9 Use of Hierarchy and Design Partitioning 75

4.2.10 Unused States in State Machines 76

4.2.12 Modular Interfaces 77

4.2.11 Glitch Sensitivity 77

4.3 Coding for Synthesis 78

4.3.1 Inferred Latches 78

4.3.2 Sensitivity Lists 79

4.3.3 Registering Module Outputs 79

4.3.4 Reset Values on Registered Signals 80

4.3.5 State Machine Coding Styles 80

4.3.7 Resource Sharing 81

4.3.6 Multiplexers and Priority 81

4.3.8 Constructs That Will Not Synthesize 83

4.4 Coding for Testability 83

4.4.1 Coding for Functional Simulation/Functional Verification 83

4.4.2 Scan-Test Issues 86

4.5 Coding for Multiple Clock Domains 87

4.5.1 Use of Multiple Clocks 87

4.5.2 Crossing Clock Boundaries 88

4.6 Summary 92

5.1 Introduction 93

Chapter 5 ASIC Simulation and Testbenches 93

5.2 Quality Testbenches 94

5.2.1 Generating Input Stimuli 95

5.2.2 Running the Tests 97

5.2.3 Comparing and Logging the Results 99

5.3 Simulation Strategy 101

5.3.1 Software Hierarchy 102

5.3.2 The Software Driver Testbench 102

5.3.3 C Model Cosimulation 103

5.3.4 Co-Verification Tool 104

5.3.5 Converting the C Code 105

5.4 Extending the Simulation Strategy 105

5.5 Reducing Top-Level Simulation Run Times 106

5.5.1 Increasing Workstation Performance 106

5.5.2 Changing Simulation Tools 107

5.5.3 Analysis of Simulation Statement Executions 107

5.5.4 Preloading RAMs 107

5.5.5 Using Behavioral Models/Test Modes 107

5.6.2 Source Code Debugging 108

5.6.1 Saving Simulation Snapshots 108

5.6 Speeding Up Debugging 108

5.5.6 Running Tests in Batch Mode 108

5.7 Different Types of Testing 109

5.7.1 Module Testing 109

5.7.2 Subsystem Testing 110

5.7.3 Chip-Level Testing 111

5.7.4 Gate-Level Testing 111

5.7.6 Board-Level Testing 112

5.8 Generation of ASIC Test Vectors 112

5.7.5 Postlayout Testing 112

5.9 Summary 113

Chapter 6 Synthesis 115

6.1 Introduction 115

6.2 The General Principle 116

6.3 Top-Down versus Bottom-Up Synthesis 116

6.4 Physical Synthesis Tools 117

6.5 Scripts versus GUIs 118

6.6 Common Steps in Synthesis Scripts 119

6.6.1 Sample Script Action Sequence 119

6.6.2 Sample Scripts 123

6.7 Directory Structures 129

6.8 Special Cells 129

6.8.1 Handling Memory Cells 129

6.8.2 I/O Cells 130

6.8.3 Other Special Cells 130

6.9 Miscellaneous Synthesis Terms,Concepts and Issues 130

6.9.1 Timing Paths 131

6.9.3 Timing Margins/Time Budgeting 132

6.9.2 Latches versus Flip-Flops 132

6.9.4 Characterize and Compile 133

6.9.5 Overconstraining Designs 133

6.9.6 Grouping and Weighting 134

6.9.7 Flattening 134

6.9.8 dont_touch Attributes 135

6.9.9 Black Boxing 135

6.10 Managing Multiple Clock Domains 135

6.11 Managing Late Changes to the Netlist 136

6.10.3 Set False Paths Across Known Asynchronous Boundaries 136

6.10.2 Identify Synchronizing Flip-Flops with Unique Names 136

6.10.1 Isolate the Asynchronous Interfaces 136

6.11.1 Complete Resynthesis 137

6.11.2 Partial Resynthesis 137

6.11.3 Editing the Gate-Level Netlist 137

6.12 Summary 138

Chapter 7 Quality Framework 139

7.1 Introduction 139

7.2 The Directory Structure 139

7.2.1 engineer_work_area 140

7.2.2 reference_files 141

7.2.3 top_level_simulations 141

7.2.4 release_area 141

7.2.5 Source Control 142

7.2.6 Synthesis Directory 142

7.2.7 Templates 142

7.3 Documentation Storage 143

7.4 Freezing Documents and Controlled Updates 143

7.5 Fault Report Database 143

7.8 Company-Defined Procedures 144

7.7 Makefiles/Simulation Scripts 144

7.6 Source Code Control 144

7.9 Summary 145

Chapter 8 Planning and Tracking ASIC Projects 147

8.1 Overview 147

8.2 Basic Planning Concepts 147

8.3 Process for Creating a Plan 150

8.3.1 Definition of Deliverables 151

8.3.2 Task Breakdown 152

8.3.3 Assigning Dependencies 153

8.3.4 Allocation of Resources 154

8.3.5 Refining the Plan 155

8.3.6 Reviewing the Plan 156

8.4 Tracking 157

8.4.1 Tracking Methods 158

8.5 Summary 159

Chapter 9 Reducing Project Risks 161

9.1 Introduction 161

9.2 Trade-Offs Between Functionality,Performance,Cost and Timescales 162

9.3 Minimizing Development Risks 163

9.3.2 ASIC Architecture 164

9.3.1 Selecting the Team 164

9.3.3 High-Level Architectural Modeling 165

9.3.4 Interface Specifications 165

9.3.5 Managing Changing Design Requirements 166

9.3.6 Programmability 166

9.3.7 Regular Design Reviews 167

9.3.8 Early Trial Synthesis 168

9.3.9 Early Trial Layouts 168

9.4 Reducing the Risk of Design Bugs 168

9.4.1 Simulation 169

9.4.2 Emulation 170

9.4.3 FPGAs 170

9.4.4 Fast-Turnaround ASICs 171

9.4.5 Early Sign-Off 172

9.5 Risks in Meeting ASIC Vendor Criteria 173

9.5.1 Power Consumption Issues 173

9.5.2 Package/Pin-Out 174

9.6 Summary 174

10.2 Using the Vendor's Expertise 177

Chapter 10 Dealing with the ASIC Vendor 177

10.1 Introduction 177

10.3 Vendor Selection 178

10.3.1 RFQ Details 179

10.3.2 Vendor Comparisons 182

10.4 ASIC Vendor Services 183

10.5 Effect of the Vendor on Timescales 184

10.5.1 Layout 184

10.5.3 Production Chips 186

10.5.4 Liaison with the Vendor During the Project 186

10.5.2 Provision of Engineering Samples 186

10.6 Summary 188

Chapter 11 Motivation and People Management 189

11.1 Introduction 189

11.2 Managing Engineers with Different Experience Levels 189

11.3 Maslow's Hierarchy of Needs 191

11.3.1 Physiological Needs and Safety Needs 191

11.3.2 Social Contact 191

11.3.3 Self-Esteem 192

11.4.1 Different Personalities 193

11.3.4 Self-Actualization 193

11.4 Getting to Know the Team 193

11.4.2 Interacting with the Impulsive Type 194

11.4.3 Interacting with the Reflective Type 195

11.5 Goal Setting 195

11.6 Communicating Project Information 196

11.6.1 Project Meetings 196

11.6.3 Competitors'Products 197

11.6.4 Highlighting the Importance of the Project to the Business 197

11.6.2 Marketing Information 197

11.6.5 Show Enthusiasm and Have Fun 198

11.7 Training 198

11.7.1 Technical Training 198

11.7.2 Personal Training 199

11.7.3 Product/Design-Specific Training 199

11.8 Summary 199

Chapter 12 The Team 201

12.1 Introduction 201

12.2.2 People-and Team-Management Skills 202

12.2 The Project Leader/Project Manager 202

12.2.1 Technical Skills 202

12.3 The Wider Team 203

12.4 Key Roles Within the Team 204

12.4.1 System Architect 204

12.4.2 Tools Expert 205

12.4.3 Testbench Engineers 205

12.4.4 Team Leaders 206

12.5 Summary 207

13.2 Running Meetings 209

Chapter 13 Project Manager Skills 209

13.1 Introduction 209

13.3 Interviewing 210

13.4 Time Management 212

13.5 Summary 213

Chapter 14 Design Tools 215

14.1 Introduction 215

14.3.2 High-Level Entry Tools 216

14.3.1 Text Editors 216

14.3 Input Tools 216

14.2 Hierarchy Tools 216

14.4 Code Analysis Tools 217

14.5 Revision Management Tools 217

14.6 Testbench and Validation Tools 217

14.6.1 Testbench Tools 218

14.6.2 Code Coverage 218

14.6.3 Standard Simulators 218

14.6.5 Hardware Accelerators 219

14.6.4 Cycle-Based Simulators 219

14.6.6 Emulation 220

14.6.7 Cosimulation 220

14.6.8 Formal Verification 220

14.7 Synthesis Tools 221

14.8 Static-Timing Analyzers 222

14.9 Summary 222

Bibliography 223

About the Authors 225

Index 227