数据转换器 英文版PDF电子书下载

1．BACKGROUND ELEMENTS 1

1.1 The Ideal Data Converter 1

1.2 Sampling 2

1.2.1 Undersampling 10

1.2.2 Sampling-time Jitter 12

1.3 Amplitude Quantization 15

1.3.1 Quantization Noise 17

1.3.2 Properties of the Quantization Noise 18

1.4 kT/C Noise 22

1.5 Discrete and Fast Fourier Transforms 25

1.5.1 Windowing 26

1.6 Coding Schemes 32

1.7 The D/A Converter 33

1.7.1 Ideal Reconstruction 34

1.7.2 Real Reconstruction 34

1.8 The Z-Transform 38

References 46

2．DATA CONVERTERS SPECIFICATIONS 47

2.1 Type of Converter 47

2.2 Conditions of Operation 48

2.3 Converter Specifications 50

2.3.1 General Features 50

2.4 Static Specifications 51

2.5 Dynamic Specifications 60

2.6 Digital and Switching Specifications 72

References 76

3．NYQUIST-RATE D/A CONVERTERS 77

3.1 Introduction 77

3.1.1 DAC Applications 79

3.1.2 Voltage and Current References 80

3.2 Types of Converters 81

3.3 Resistor based Architectures 82

3.3.1 Resistive Divider 83

3.3.2 X-Y Selection 85

3.3.3 Settling of the Output Voltage 86

3.3.4 Segmented Architectures 89

3.3.5 Effect of the Mismatch 91

3.3.6 Trimming and Calibration 94

3.3.7 Digital Potentiometer 97

3.3.8 R-2R Resistor Ladder DAC 97

3.3.9 Deglitching 106

3.4 Capacitor Based Architectures 107

3.4.1 Capacitive Divider DAC 107

3.4.2 Capacitive MDAC 110

3.4.3 "Flip Around"MDAC 112

3.4.4 Hybrid Capacitive-Resistive DACs 113

3.5 Current Source based Architectures 114

3.5.1 Basic Operation 114

3.5.2 Unity Current Generator 118

3.5.3 Random Mismatch with Unary Selection 121

3.5.4 Current Sources Selection 122

3.5.5 Current Switching and Segmentation 124

3.5.6 Switching of Current Sources 129

3.6 Other Architectures 131

References 139

4．NYQUIST RATE A/D CONVERTERS 141

4.1 Introduction 141

4.2 Timing Accuracy 143

4.2.1 Metastability error 146

4.3 Full-Flash Converters 147

4.3.1 Reference Voltages 148

4.3.2 Offset of Comparators 150

4.3.3 Offset Auto-zeroing 152

4.3.4 Practical Limits 155

4.4 Sub-Ranging and Two-Step Converters 157

4.4.1 Accuracy Requirements 159

4.4.2 Two-step Converter as a Non-linear Process 164

4.5 Folding and Interpolation 165

4.5.1 Double Folding 166

4.5.2 Interpolation 167

4.5.3 Use of Interpolation in Flash Converters 169

4.5.4 Use of Interpolation in Folding Architectures 170

4.5.5 Interpolation for Improving Linearity 171

4.6 Time-Interleaved Converters 174

4.6.1 Accuracy requirements 175

4.7 Successive Approximation Converter 178

4.7.1 Errors and Error Correction 180

4.7.2 Charge Redistribution 182

4.8 Pipeline Converters 184

4.8.1 Accuracy Requirements 187

4.8.2 Digital Correction 188

4.8.3 Dynamic Performances 194

4.8.4 Sampled-data Residue Generator 198

4.9 Other Architectures 199

4.9.1 Cyclic(or Algorithmic)Converter 199

4.9.2 Integrating Converter 200

4.9.3 Voltage-to-Frequency Converter 202

References 207

5．CIRCUITS FOR DATA CONVERTERS 209

5.1 Sample-and-Hold 209

5.2 Diode Bridge S＆H 210

5.2.1 Diode Bridge Imperfections 211

5.2.2 Improved Diode Bridge 212

5.3 Switched Emitter Follower 213

5.3.1 Circuit Implementation 215

5.3.2 Complementary Bipolar S＆H 216

5.4 Features of S＆Hs with BJT 217

5.5 CMOS Sample-and-Hold 222

5.5.1 Clock Feed-through 224

5.5.2 Clock Feed-through Compensation 226

5.5.3 Two-stages OTA as T＆H 227

5.5.4 Use of the Virtual Ground in CMOS S＆H 229

5.5.5 Noise Analysis 230

5.6 CMOS Switch with Low Voltage Supply 235

5.6.1 Switch Bootstrapping 238

5.7 Folding Amplifiers 240

5.7.1 Current-Folding 240

5.7.2 Voltage Folding 242

5.8 Voltage-to-Current Converter 243

5.9 Clock Generation 247

References 251

6．OVERSAMPLING AND LOW ORDER ∑△ MODULATORS 253

6.1 Introduction 253

6.1.1 Delta and Sigma-Delta Modulation 255

6.2 Noise Shaping 256

6.3 First Order Modulator 258

6.3.1 Intuitive Views 262

6.3.2 Use of 1-bit Quantization 264

6.4 Second Order Modulator 265

6.5 Circuit Design Issues 267

6.5.1 Offset 268

6.5.2 Finite Op-Amp Gain 268

6.5.3 Finite Op-Amp Bandwidth 272

6.5.4 Finite Op-Amp Slew-Rate 273

6.5.5 ADC Non-ideal Operation 275

6.5.6 DAC Non-ideal Operation 275

6.6 Architectural Design Issues 276

6.6.1 Integrator Dynamic Range 276

6.6.2 Dynamic Ranges Optimization 281

6.6.3 Sampled-data Circuit Implementation 288

6.6.4 Noise Analysis 289

6.6.5 Quantization Error and Dithering 294

6.6.6 Single-bit and Multi-bit 296

References 301

7．HIGH-ORDER,CT ∑△ CONVERTERS AND ∑△ DAC 303

7.1 SNR Enhancement 303

7.2 High Order Noise Shaping 306

7.2.1 Single Stage Architectures 308

7.2.2 Stability Analysis 309

7.2.3 Weighted Feedback Summation 311

7.2.4 Modulator with Local Feedback 314

7.2.5 Chain of Integrators with Distributed Feedback 316

7.2.6 Cascaded ∑△ Modulator 317

7.2.7 Dynamic range for MASH 322

7.3 Continuous-time ∑△ Modulators 325

7.3.1 S＆H Limitations 326

7.3.2 CT Implementations 328

7.3.3 Design of CT from Sampled-Data Equivalent 333

7.4 Band-Pass ∑△ Modulator 335

7.4.1 Interleaved N-Path Architecture 339

7.4.2 Synthesis of the NTF 344

7.5 Oversampling DAC 346

7.5.1 1-bit DAC 347

7.5.2 Double Return-to-zero DAC 350

References 356

8．DIGITAL ENHANCEMENT TECHNIQUES 359

8.1 Introduction 359

8.2 Error Measurement 360

8.3 Trimming of Elements 362

8.4 Foreground Calibration 364

8.5 Background Calibration 367

8.5.1 Gain and Offset in Interleaved Converters 370

8.5.2 Offset Calibration without Redundancy 371

8.6 Dynamic Matching 374

8.6.1 Butterfly Randomization 377

8.6.2 Individual Level Averaging 381

8.6.3 Data Weighted Averaging 385

8.7 Decimation and Interpolation 391

8.7.1 Decimation 391

8.7.2 Interpolation 395

References 399

9．TESTING OF D/A AND A/D CONVERTERS 401

9.1 Introduction 401

9.2 Test Board 403

9.3 Quality and Reliability Test 405

9.4 Data Processing 407

9.4.1 Best-fit-line 407

9.4.2 Sine Wave Fitting 408

9.4.3 Histogram Method 409

9.5 Static DAC Testing 413

9.5.1 Transfer Curve Test 414

9.5.2 Superposition of Errors 414

9.5.3 Non-linearity Errors 416

9.6 Dynamic DAC Testing 416

9.6.1 Spectral Features 417

9.6.2 Conversion Time 419

9.6.3 Glitch Energy 420

9.7 Static ADC Testing 421

9.7.1 Code Edge Measurement 423

9.8 Dynamic ADC Testing 424

9.8.1 Time Domain Parameters 425

9.8.2 Improving the Spectral Purity of Sine Waves 426

9.8.3 Aperture Uncertainty Measure 428

9.8.4 Settling-time Measure 430

9.8.5 Use of FFT for Testing 431

References 434

Index 435