数字原理与设计PDF电子书下载

1.1 The Digital Age 1

Chapter 1 Introduction 1

1.2 Analog and Digital Representations of Information 2

1.3 The Digital Computer 2

9.4 The Primitive Flow Table 3

9.5 Reduction of Input-Restricted Flow Tables 3

9.5.1 Determination of Compatible Pairs of States 3

9.5.2 Dctermination of Maximal Compatibles 3

9.5.3 Determination of Minimal Collections of Maximal Compatible Sets9.5.4 Constructing the Minimal-Row Flow Table9.6 A General Procedure to Flow Table Reduction9.6.1 Reducing the Number of Stable States9.6.2 Merging the Rows of a Primitive Flow 3

9.4.1 The Primitive Flow Table for Example 9. 3

1.3.1 The Organization of a Digital Computer 3

9.7.2 The Transition Table for Example 9. 4

9.4.2 The Primitive Flow Table for Example 9. 4

1.4 An Overview 5

1.3.2 The Operation of a Digital Computer 5

2.1 Positional Number Systems 7

Chapter 2 Number Systems,Arithmetic,and Codes 7

2.2 Counting in a Positional Number System 9

2.3 Basic Arithmetic Operations 11

2.3.2 Subtraction 11

2.3.1 Addition 11

2.3.3 Multiplication 14

2.4 Polynomial Method of Number Conversion 16

2.3.4 Division 16

2.5 Iterative Method of Number Conversion 19

2.5.1 Iterative Method for Converting Integers 20

2.5.2 Verification of the Iterative Method for Integers 21

2.5.3 Iterative Method for Converting Fractions 22

2.5.5 A Final Example 23

2.5.4 Verification of the Iterative Method for Fractions 23

2.6 Special Conversion Procedures 24

2.7 Signed Numbers and Complements 26

2.8 Addition and Subtraction with r's-Complements 31

2.8.1 Signed Addition and Subtraction 33

2.9.1 Signed Addition and Subtraction 36

2.10 Codes 36

2.9 Addition and Subtraction with(r-1)'s-Complements 36

2.10.1 Decimal Codes 37

2.10.2 Unit-Distance Codes 40

2.10.3 Alphanumeric Codes 42

2.11 Error Detection 43

Problems 45

2.12 Error Correction 45

2.12.3 Check Sum Digits for Error Correction 45

2.12.2 Single-Error Correction plus Double-Error Detection 45

2.12.1 Hamming Code 45

Chapter 3 Boolean Algebra and Combinational Networks 53

3.1 Definition of a Boolean Algebra 54

3.1.1 Principle of Duality 55

3.2 Boolean Algebra Theorems 55

3.3 A Two-Valued Boolean Algebra 62

3.4 Boolean Formulas and Functions 65

3.4.1 Normal Formulas 67

3.5 Canonical Formulas 68

3.5.1 Minterm Canonical Formulas 68

3.5.2 m-Notation 70

3.5.3 Maxterm Canonical Formulas 72

3.5.4 M-Notation 73

3.6.1 Equation Complementation 75

3.6 Manipulations of Boolean Formulas 75

3.6.2 Expansion about a Variable 76

3.6.3 Equation Simplification 76

3.6.4 The Reduction Theorems 78

3.6.5 Minterm Canonical Formulas 79

3.6.6 Maxterm Canonical Formulas 80

3.6.7 Complements of Canonical Formulas 81

3.7 Gates and Combinational Networks 83

3.7.2 Combinational Networks 84

3.7.1 Gates 84

3.7.3 Analysis Procedure 85

3.7.4 Synthesis Procedure 86

3.7.5 A Logic Design Example 87

3.8 Incomplete Boolean Functions and Don't-Care Conditions 89

3.8.1 Describing Incomplete Boolean Functions 91

3.8.2 Don't-Care Conditions in Logic Design 91

3.9 Additional Boolean Operations and Gates 93

3.9.1 The Nand-Function 94

3.9.3 Universal Gates 95

3.9.2 The Nor-Function 95

3.9.4 Nand-Gate Realizations 97

3.9.5 Nor-Gate Realizations 100

3.9.6 The Exclusive-Or-Function 103

3.10 Gate Properties 105

3.9.7 The Exclusive-Nor-Function 105

3.10.1 Noise Margins 107

3.10.2 Fan-Out 108

3.10.3 Propagation Delays 109

Problems 110

3.10.4 Power Dissipation 110

4.1 Formulation of the Simplification Problem 119

Chapter 4 Simplification of Boolean Expressions 119

4.1.1 Criteria of Minimality 120

4.1.2 The Simplification Problem 121

4.2 Prime Implicants and Irredundant Disjunctive Expressions 121

4.2.1 Implies 121

4.2.2 Subsumes 122

4.2.3 Implicants and Prime Implicants 123

4.2.4 Irredundant Disjunctive Normal Formulas 125

4.3 Prime Implicates and Irredundant Conjunctive Expressions 125

4.4.1 One-Variable and Two-Variable Maps 127

4.4 Karnaugh Maps 127

4.4.2 Three-Variable and Four-Variable Maps 128

4.4.3 Karnaugh Maps and Canonical Formulas 130

4.4.4 Product and Sum Tern Representations on Karnaugh Maps 133

4.5.1 Prime Implicants and Karnaugh Maps 137

4.5 Using Karnaugh Maps to Obtain Minimal Expressions for Complete Boolean Functions 137

4.5.2 Essential Prime Implicants 142

4.5.3 Minimal Sums 143

4.5.4 Minimal Products 147

4.6 Minimal Expressions of Incomplete Boolean Functions 149

4.6.1 Minimal Sums 150

4.6.2 Minimal Products 151

4.7.2 Six-Variable Maps 152

4.7 Five-Variable and Six-Variable Karnaugh Maps 152

4.7.1 Five-Variable Maps 152

4.8 The Quine-McCluskey Method of Generating Prime Implicants and Prime Implicates4.8.1 Prime Implicants and the Quine-McCluskey Method4.8.2 Algorithm for Generating Prime Implicants4.8.3 Prime Implicates and the Quine-McCluskey Method4.9 Prime-Impl 152

Chapter 5 Logic Design with MSI Components and Programmable Logic Devices 160

5.1　Binary Adders and Subtracters 161

5.1.1 Binary Subtracters 163

5.1.2 Carry Lookahead Adder 166

5.1.3 Large High-Speed Adders Using the Carry Lookahead Principle 168

5.2 Decimal Adders 172

5.3 Comparators 176

5.4 Decoders 178

5.4.1 Logic Design Using Decoders 179

5.4.2 Decoders with an Enable Input 186

5.5 Encoders 190

5.6 Multiplexers 192

5.6.1 Logic Design with Multiplexers 196

5.7 Programmable Logic Devices(PLDs) 206

5.7.1 PLD Notation 209

5.8 Programmable Read-Only Memories(PROMs) 209

5.9 Programmable Logic Arrays(PLAs) 213

5.10 Programmable Array Logic(PAL)Devices 222

Problems 224

Chapter 6 Flip-Flops and Simpie Flip-Flop Applications 231

6.1 The Basic Bistable Element 232

6.2 Latches 233

6.2.1 The SR Latch 234

6.2.2 An Application of the SR Latch:A Switch Debouncer 235

6.2.3 The SR Latch 237

6.2.4 The Gated SR Latch 238

6.2.5 The Gated D Latch 239

6.3 Timing Considerations 240

6.3.1 Propagation Delays 240

6.3.2 Minimum Pulse Width 242

6.3.3 Setup and Hold Times 242

6.4 Master-Slave Flip-Flops(Pulse-Triggered Flip-Flops) 243

6.4.1 The Master-Slave SR Flip-Flop 244

6.4.2 The Master-Slave JK Flip-Flop 247

6.4.3 0's and 1's Catching 249

6.4.4 Additional Types of Master-Slave Flip-Flops 250

6.5.1 The Positive-Edge-Triggered D Flip-Flop 251

6.5 Edge-Triggered Flip-Flops 251

6.5.2 Negative-Edge-Triggered D Flip-Flops 254

6.5.3 Asynchronous Inputs 254

6.5.4 Additional Types of Edge-Triggered Flip-Flops 256

6.5.5 Master-Slave Flip-Flops with Data Lockout 258

6.6 Characteristic Equations 259

6.7 Registers 262

6.8.1 Binary Ripple Counters 267

6.8 Counters 267

6.8.2 Synchronous Binary Counters 270

6.8.3 Counters Based on Shift Registers 275

6.9 Design of Synchronous Counters 277

6.9.1 Design of a Synchronous Mod-6 Counter Using Clocked JK Flip-Flops 278

6.9.2 Design of a Synchronous Mod-6 Counter Using Clocked D,T,or SR Flip-Flops 282

6.9.3 Self-Correcting Counters 286

Problems 288

Chapter 7 Synchronous Sequential Networks 297

7.1 Structure and Operation of Clocked Synchronous Sequential Networks 298

7.2 Analysis of Clocked Synchronous Sequential Networks 301

7.2.1 Excitation and Output Expressions 303

7.2.2 Transition Equations 304

7.2.3 Transition Tables 305

7.2.4 Excitation Tables 307

7.2.5 State Tables 309

7.2.6 State Diagrams 310

7.2.7 Network Terminal Behavior 312

7.3 Modeling Clocked Synchronous Sequential Network Behavior 315

7.3.1 The Serial Binary Adder as a Mealy Network 315

7.3.2 The Serial Binary Adder as a Moore Network 318

7.3.3 A Sequence Recognizer 320

7.3.4 A 0110/1001 Sequence Recognizer 323

7.3.5 A Final Example 326

7.4 State Table Reduction 328

7.4.1 Determining Equivalent Pairs of States 329

7.4.2 Obtaining the Equivalence Classes of States 335

7.4.3 Constructing the Minimal State Table 336

7.4.4 The 0110/1001 Sequence Recognizer 340

7.5 The State Assignment 345

7.5.1 Some Simple Guidelines for Obtaining State Assignments 348

7.5.2 Unused States 352

7.6 Completing the Design of Clocked Synchronous Sequential Networks 354

7.6.1 Realizations Using Programmable Logic Devices 362

Problcms 366

Chapter 8 Algorithmic State Machines 374

8.1 The Algorithmic State Machine 374

8.2 ASM Charts 377

8.2.1 The State Box 378

8.2.2 The Decision Box 379

8.2.4 ASM Blocks 380

8.2.3 The Conditional Output Box 380

8.2.5 ASM Charts 386

8.2.6 RelationshiP between State Diagrams and ASM Charts 389

8.3.1 A Sequence Recognizer 391

8.3 Two Examples of Synchronous Sequential Network Design Using ASM Charts 391

8.3.2 A Parallel(Unsigned)Binary Multiplier 393

8.4 State Assignments 398

8.5 ASM Tables 400

8.5.1 ASM Transition Tables 400

8.5.2 Assigned ASM Transition Tables 402

8.5.3 Algebraic Representation of Assigned Transition Tables 405

8.5.4 ASM Excitation Tables 407

8.6.1 Realizations Using Discrete Gates 409

8.6 ASM Realizations 409

8.6.2 Realizations Using Multiplexers 414

8.6.3 Realizations Using PLAs 417

8.6.4 Realizations Using PROMs 420

8.7 Asynchronous Inputs 421

Problems 423

Chapter 9 Asynchronous Sequential Networks 435

9.1 Structure and Operation of Asynchronous Sequential Networks 436

9.2 Analysis of Asynchronous Sequential Networks 440

9.2.1 The Excitation Table 442

9.2.2 The Transition Table 444

9.2.3 The State Table 446

9.2.4 The Flow Table 447

9.2.5 The Flow Diagram 449

9.3 Races in Asynchronous Sequential Networks 450

9.7.3 The Need for Additional State Variables 452

9.7.4 A Systematic State-Assignment Procedure 452

9.8 Completing the Asynchronous Sequential Network Design 452

9.9 Static and Dynamic Hazards in Combinational Networks 452

9.9.1 Static Hazards 453

9.9.2 Detecting Static Hazards 455

9.9.3 Eliminating Static Hazards 459

9.9.4 Dynamic Hazards 461

9.9.6 Hazards in Asynchronous Networks Involving Latches 462

9.9.5 Hazard-Free Combinational Logic Networks 462

9.10 Essential Hazards 464

9.10.1 Example of an Essential Hazard 465

9.10.2 Detection of Essential Hazards 466

Problems 469

Bibliography 480

翻译版目录 483

第1章 绪论 483

1.1 数字时代 483

1.2 信息的模拟和数字表示 484

1.3 数字计算机 484

1.3.1 数字计算机的结构 485

1.3.2 数字计算机的操作 486

1.4 概述 487

第2章 数制系统，算术和编码 488

2.1 位置数制系统 488

2.2 位置数制系统中的计数 490

2.3 基本算术操作 491

2.3.1 加法 491

2.3.2 减法 493

2.3.3 乘法 494

2.3.4 除法 496

2.4 数制转换的多项式法 496

2.5 数制转换的迭代法 499

2.5.1 整数转换的迭代法 499

2.5.3 小数转换的迭代法 500

2.5.2 整数迭代法的证明 500

2.5.4 小数迭代法的证明 501

2.5.5 最后举例 501

2.6 特殊转换过程 502

2.7 有符号数和补数 503

2.8 r补数的加法和减法 507

2.9 r-1补数的加法和减法 511

2.10 编码 511

2.10.1 十进制编码 511

2.10.2 单位距离编码 514

2.10.3 字符编码 516

2.11 错误检测 517

第3章 布尔代数和组合网络 519

3.1 布尔代数的定义 520

3.2 布尔代数诸定理 521

3.3 二值布尔代数 527

3.4 布尔公式和函数 529

3.5 规范公式 531

3.5.1 最小项规范公式 532

3.5.2 m标记 533

3.5.3 最大项规范公式 534

3.5.4 M标记 535

3.6 布尔公式的处理 537

3.6.1 方程求补 537

3.6.2 变量扩展 538

3.6.3 方程化简 539

3.6.4 简化定理 540

3.6.5 最小项规范公式 541

3.6.6 最大项规范公式 542

3.6.7 规范公式的反函数 543

3.7 门和组合网络 544

3.7.1 门 545

3.7.2 组合网络 545

3.7.3 分析过程 546

3.7.4 综合过程 547

3.7.5 逻辑设计实例 548

3.8 不完全确定布尔函数和无关条件 549

3.8.2 逻辑设计中的无关项条件 551

3.8.1 描述不完全确定布尔函数 551

3.9 其他布尔运算和门 553

3.9.1 与非函数 553

3.9.2 或非函数 554

3.9.3 通用门 555

3.9.4 与非门实现 556

3.9.5 或非门实现 559

3.9.6 异或函数 561

3.9.7 异或非函数 563

3.10 门特性 563

3.10.1 噪声容限 564

3.10.4 功耗 566

3.10.2 扇出 566

3.10.3 传输延时 566

第4章 布尔表达式的化简 567

4.1 化简问题的表述 567

4.1.1 最简化的准则 567

4.1.2 化简问题 568

4.2 质蕴含项和非冗余析取表达式 569

4.2.1 蕴含 569

4.2.2 包含 570

4.2.3 蕴含项和质蕴含项 570

4.2.4 非冗余析取正则表达式 572

4.3 质包含项和非冗余合取表达式 572

4.4 卡诺图 573

4.4.1 单变量和两变量卡诺图 574

4.4.2 三变量和四变量卡诺图 574

4.4.3 卡诺图和规范公式 577

4.4.4 卡诺图中与项和或项的表示 578

4.5 使用卡诺图得到完全确定布尔函数的最简表达式 583

4.5.1 质蕴含项和卡诺图 583

4.5.2 基本质蕴含项 586

4.5.3 最简或形式 587

4.5.4 最简与形式 590

4.6 不完全确定布尔函数的最简表达式 592

4.6.1 最简或形式 592

4.6.2 最简与形式 593

第5章 使用MSI元件和可编程逻辑器件的逻辑设计 595

5.1 二进制加法器和减法器 596

5.1.1 二进制减法器 598

5.1.2 超前进位加法器 600

5.1.3 利用超前进位原理实现大型高速加法器 602

5.2 十进制加法器 606

5.3 比较器 609

5.4 译码器 612

5.4.1 使用译码器的逻辑设计 612

5.4.2 有使能输入的译码器 619

5.5 编码器 622

5.6 复用器 623

5.7 可编程逻辑器件 635

5.8 可编程只读存储器 638

5.9 可编程逻辑阵列 641

5.10 可编程阵列逻辑器件 649

第6章 触发器及其简单应用 652

6.1 双稳态基本单元 653

6.2 锁存器 654

6.2.1 SR锁存器 654

6.2.2 一种SR锁存器的应用：开关去反弹器 656

6.2.3 SR锁存器 657

6.2.4 门控SR锁存器 658

6.2.5 门控D锁存器 659

6.3.1 传输延时 660

6.3 触发器时序的考虑 660

6.3.2 最小脉冲宽度 662

6.3.3 建立和保持时间 662

6.4 主从触发器 663

6.4.1 主从型SR触发器 664

6.4.2 主从型JK触发器 666

6.4.3 0信号和1信号的捕获 669

6.4.4 其他类型的主从型触发器 670

6.5 边沿触发的触发器 671

6.5.1 正边沿触发D触发器 671

6.5.2 负边沿触发D触发器 673

6.5.3 异步输入信号 674

6.5.4 其他类型的边沿触发的触发器 675

6.5.5 具有数据锁存功能的主从型触发器 677

6.6 特征方程 678

6.7 寄存器 680

6.8 计数器 685

6.8.1 二进制逐次进位计数器 685

6.8.2 同步二进制计数器 687

6.8.3 基于移位寄存器的计数器 692

6.9 同步计数器的设计 693

6.9.1 用钟控JK触发器设计模6同步计数器 694

6.9.2 使用钟控D、T以及SR触发器的模6同步计数器的设计 698

6.9.3 自启动的计数器 701

第7章 同步时序网络 703

7.1 钟控同步时序网络的结构和操作过程 704

7.2 钟控同步时序网络的分析 706

7.2.1 激励和输出方程 708

7.2.2 转换方程 708

7.2.3 转换表 709

7.2.4 激励表 711

7.2.5 状态表 712

7.2.6 状态图 713

7.2.7 网络的最终行为 714

7.3 钟控同步时序网络的行为的建模 716

7.3.1 米利型串行二进制加法器 717

7.3.2 摩尔型串行二进制加法器 719

7.3.3 序列检测器 720

7.3.4 0110/1001序列检测器 722

7.3.5 总结举例 725

7.4 状态表的化简 726

7.4.1 确定等价状态对 727

7.4.2 获得等价状态类 732

7.4.3 建立最小状态表 733

7.4.4 0110/1001序列检测器 736

7.5 状态分配 741

7.5.1 状态分配的一些简单指导原则 744

7.5.2 未用状态 747

7.6 完成钟控同步时序网络的设计 749

附录A 中英文名词索引 760