嵌入式微控制器与处理器设计 英文版PDF电子书下载

CHAPTER 1 EMBEDDED PROCESSORS 1

1.0 Microcontrollers 1

1.1 Microcontroller Markets 1

1.2 Data Path 2

1.3 Commercial Microcontrollers 2

1.4 SoC Core Processors 2

1.5 Relative SoC Unit Volumes 3

1.6 Very-Large-Scale Integration(VLSI)Chip Design Tools 4

1.7 Intellectual Property 4

1.8 Instruction Set Architecture 6

1.9 Return on Investment 6

1.10 Semiconductor Technology Developments 7

CHAPTER 2 MICROCONTROLLER ARCHITECTURE 11

2.0 Computer on a Chip 11

2.1 John yon Neumann 12

2.1.1 von Neumann Architecture 12

2.2 Computer Architectures 13

2.2.1 CISC and RISC 13

2.3 Semiconductor Technology 14

2.3.1 Small-Scale Integration 14

2.3.2 Hardware Bus 14

2.3.3 Intelligent Peripherals 15

2.3.4 Standardized I/O Interfaces 15

2.4 MSI and LSI 16

2.5 Electronic Calculator 17

2.5.1 Programmable Calculator 17

2.6 Microprocessors 18

2.6.1 Application-Oriented Processing 18

2.6.2 Intel i4004 19

2.6.3 Intel i8080 19

2.7 Microprocessor Peripherals 20

2.7.1 Microcomputer 20

2.8 i8051 Microcontroller 21

2.9 RISC Introduction 22

2.9.1 RISC Processors 22

2.9.2 RISC Synergy 23

2.9.3 RISC Marketing 24

2.10 Fabless Semiconductor Company 24

2.10.1 RISC as Intellectual Property 25

2.10.2 RISC Technology Curve 25

2.11 Embedded Controller IP 26

2.11.1 CISC IP 27

2.11.2 RISC IP 27

2.11.3 Third-Party IP 27

2.12 Application Specific Processors 27

2.13 Summary 28

CHAPTER 3 EMBEDDED MICROCONTROLLER TECHNOLOGY 30

3.0 Integrated Circuits 30

3.1 Moore's Law 30

3.1.1 Microprocessor Performance 31

3.1.2 Enabling Technologies 32

3.1.3 Amdahl's Law 33

3.1.4 Technology Convergence 33

3.2 Design Abstraction 34

3.2.1 Instruction Set Architectures 34

3.2.2 Processor Family Tree 35

3.3 RISC and CISC 35

3.3.1 Processor Technology 36

3.3.2 Performance Measurement 36

3.3.3 Program Instructions 36

3.3.4 Cost per Instruction 37

3.3.5 Microcoded Instructions 37

3.4 Memory Technology 38

3.4.1 Locality 39

3.4.2 Memory Hierarchy 39

3.4.3 Cache Memory 40

3.4.4 L1 and L2 Cache 40

3.4.5 Data Registers 41

3.4.6 Instruction Queues 41

3.4.7 Branch Instructions 41

3.4.8 Memory Latency 42

3.4.9 Cache Blocks 42

3.5 Instruction Processing 44

3.5.1 Symbolic Assembly 44

3.5.2 Program Compilers 45

3.5.3 Hard-Coded Instructions 45

3.6 Program Design 45

3.6.1 Program Code Size Creep 46

3.6.2 CISC Instruction Set 46

3.7 Unified Instruction Set 47

3.7.1 Industry Standard Software 47

3.7.2 Instruction Set Extensions 47

3.8 RISC Instruction Set Architecture 48

3.8.1 Microcode 48

3.8.2 Micro Instruction Cycles 48

3.8.3 Application Specific Instructions 48

3.8.4 Single-Cycle Instructions 49

3.9 Processor Logic 49

3.9.1 Synchronous Logic 50

3.9.2 Register Sets 50

3.9.3 Orthogonal Registers 50

3.9.4 Register Optimization 50

3.9.5 Load/Store Data Operations 51

3.10 Processor Functional Partitioning 51

3.10.1 Instruction Pipelining 51

3.10.2 Execution Units 52

3.10.3 Pipeline Stages 52

3.10.4 Pipeline Throughput 53

3.10.5 Sequential Execution 54

3.10.6 Branch Execution 54

3.11 Five-Stage Pipeline 54

3.11.1 Instruction Pipeline Stalls 56

3.11.2 Branch Prediction Table 56

3.11.3 Data Pipeline Stall 56

3.12 Summary 56

CHAPTER 4 MICROCONTROLLER FUNCTIONS 58

4.0 Device Functions 58

4.1 Transistor Technology 59

4.1.1 CMOS Transistor 59

4.1.2 CMOS Power Consumption 60

4.1.3 Packaging 60

4.1.4 Operating Temperature Range 61

4.2 Memory Technologies 61

4.2.1 DRAM 62

4.2.2 SRAM 62

4.2.3 NVRWM 63

4.2.4 EEPROM 63

4.2.5 FLASH Technology 64

4.2.6 ROM 64

4.3 Hardware Features 64

4.3.1 Configuration Word 64

4.3.2 Oscillator Types 65

4.3.3 Reset 66

4.3.4 Standby Modes 66

4.3.5 Low-Power Consumption 67

4.3.6 Watchdog Timer 67

4.3.7 In-Circuit Programming 67

4.4 Data Input/Output 68

4.4.1 Parallel I/O 68

4.4.2 Tri-State Bit I/O 69

4.4.3 Memory Mapped I/O 69

4.5 Synchronous Serial Communication 70

CHAPTER 5 PROGRAM DESIGN 72

5.0 Program Design 72

5.1 Polling Program 73

5.1.1 Program Flow 73

5.1.2 Program Timing 74

5.1.3 Sequential Tasks 74

5.1.4 Task Timing 75

5.1.5 Multiple Sequential Tasks 76

5.2 Interrupts 76

5.2.1 Asynchronous Timing 77

5.2.2 Interrupt Enable 77

5.2.3 Machine State 78

5.2.4 Latency 78

5.2.5 Context Switch 79

5.2.6 Interrupt Vector 79

5.2.7 Nested Interrupts 80

5.2.8 Critical Code 80

5.2.9 Interrupt Service Routine 82

5.3 Real-Time Operating System 82

5.4 Event-Driven System 83

5.5 Nucleus 83

5.6 System Layering 84

5.7 Risk 84

CHAPTER 6 HARDWARE/SOFTWARE DEBUG 86

6.0 Hardware/Software Debug 86

6.1 COTS Controller Tools 87

6.2 Embedded Controller Tools 88

6.3 First Silicon 88

6.4 Bpard-Level Probes 89

6.5 Debug Process Steps 90

6.5.1 Software Editor 90

6.5.2 Compilation 91

6.5.3 Program Build 92

6.5.4 Simulator 92

6.5.5 In-Circuit Emulation 93

6.6 SoC Debug Strategies 94

6.6.1 SoC Software Debug 95

6.6.2 Core-Level Debug 95

6.6.3 JTAG/EJTAG Specification 96

6.7 ARM SoC Debug 96

6.8 MIPS SoC Debug 98

6.8.1 EJTAG Functions 99

CHAPTER 7 SERIAL DATA COMMUNICATIONS 101

7.0 Serial Data Communication 101

7.1 UART 101

7.1.1 Asynchronous Mode 102

7.1.2 Transmit/Receive Buffers 104

7.2 SPI-Serial Peripheral Interface 105

7.3 I2C-Inter-IC Bus 108

7.3.1 How the I2C Bus Works 109

7.3.2 I2C Bus Terminology 110

7.3.3 Terminology for Bus Transfer 111

7.4 CAN—Controller Area Network 112

7.5 LIN—Local Interconnect Network 115

7.6 I2S—Inter-IC Sound 116

7.6.1 I2S Serial Data 117

7.6.2 I2S Word Select 117

7.6.3 I2S Bus Timing 117

7.7 IrDA-Infrared Data Association 118

7.7.1 IrDA Stack 119

7.8 USB-Universal Peripheral Bus 119

7.8.1 USB Topology 120

7.8.2 USB Architecture 121

7.8.3 USB Physical Connection 122

7.8.4 USB Interface 122

7.8.5 USB 2.0 Specification 122

7.9 Bluetooth 122

7.9.1 Bluetooth Architecture 124

7.9.2 Bluetooth Frequency 124

7.9.3 Bluetooth Network 125

CHAPTER 8 ANALOG TO DIGITAL CONVERSION 127

8.0 Analog-to-Digital Conversion 127

8.1 Analog-to-Digital Conversion Overview 127

8.2 Transducers 129

8.3 Low-Pass Filter 130

8.3.1 Active Filter 131

8.4 Sampling 131

8.5 Shannon's Sampling Theorem 132

8.6 Whatis an ADC? 133

8.6.1 ADC Converter Resolution 134

8.6.2 LSB and MSB Defined 134

8.6.3 Quantization 135

8.6.4 Quantization Error 137

8.6.5 Offset Error 138

8.6.6 Differential Nonlinearity 139

8.6.7 Missing Codes 139

8.6.8 SNR—Signal-to-Noise Ratio 140

8.7 Analog-to-Digital Conversion Algorithms 141

8.7.1 Successive Approximation 142

8.7.2 SAR ADC Architecture 142

8.7.3 Flash ADC 145

8.7.4 Integrating ADCs 146

8.7.4.1 Single-Slope Architecture 146

8.7.4.2 Dual-Slope Architecture 147

8.7.5 Pipeline ADC 148

8.7.6 Sigma-Delta 149

8.8 Oversampling 150

CHAPTER 9 DIGITAL SIGNAL PROCESSING 153

9.0 Digital Signal Processing 153

9.1 Whatis a DSP? 154

9.1.1 Filtering and Synthesis 155

9.1.2 DSP Performance 155

9.1.3 Analog Signal Conversion 156

9.2 DSP Controller Architectures 156

9.3 Analog Filters 159

9.3.1 Filter Performance Measurements 159

9.3.2 Time Domain Response 161

9.3.3 Analog Low-Pass Filter 161

9.3.4 Active Analog Filters 162

9.3.5 Active Filter Comparison 163

9.4 Digital Filters 164

9.4.1 Finite Input Response Filter 164

9.4.2 FIR Filter Implementation 166

9.4.3 Convolution 167

9.4.4 Infinite Impulse Response Filter 169

9.5 Signal Transformation 170

9.5.1 Phasor Model 170

9.5.2 Fourier Series 171

9.5.3 Discrete Fourier Series 171

9.5.4 Fourier Transform 171

9.5.5 Discrete Fourier Transform 172

9.6 Fast Fourier Transform 174

9.6.1 FFT Implementation 174

9.6.2 DFT"Butterfly" 175

9.7 Table Addressing 176

CHAPTER 10 FUZZY LOGIC 178

10.0 Fuzzy Logic 178

10.1 Fuzzy Logic Method 180

10.2 Fuzzy Perception 180

10.3 Fuzzy Logic Terminology 181

10.4 Fuzzy Expert System 182

10.4.1 The Inference Process 183

10.4.2 Fuzzification 183

10.4.3 Inference 184

10.4.4 Composition 184

10.4.5 Defuzzification 185

10.5 Linguistic Variables 185

10.5.1 Using Linguistic Variables 187

10.5.2 Anatomy of a Fuzzy Rule 188

10.5.3 Logically Combining Linguistic Variables 188

10.6 PID Controller 189

10.6.1 Linguistic Time of Day 189

10.6.2 Linguistic Comparisons 190

10.7 Fuzzy Logic Application 191

10.7.1 How Fuzzy Logic is Used 191

10.8 The Rule Matrix 192

10.8.1 Fuzzy Logic Implementation 193

10.8.2 Membership Functions 194

10.8.3 Input Degree of Membership 197

10.8.4 Inferencing 197

10.9 Defuzzification 198

10.9.1 Fuzzy Centroid Algorithm 198

10.10 Tuning and System Enhancement 199

CHAPTER 11 8-BIT MICROCONTROLLERS 201

11.0 General-Purpose Microcontrollers 201

11.1 MicroChip PIC18F4520 202

11.1.1 PIC18F4520 Harvard Architecture 202

11.1.2 Instruction Pipeline 204

11.1.3 Special Features 205

11.1.4 Power Management Modes 205

11.1.5 Oscillator Configuration 206

11.1.6 Reset 207

11.1.7 Memory Organization 208

11.1.8 Interrupt Structure 210

11.1.9 Input/Output Ports 211

11.1.10 Timer-Related Functions 211

11.1.11 Timer Modules 212

11.1.12 Capture/Compare/PWM Functions 215

11.1.13 Serial Communication Interface 218

11.1.13.1 MSSP 218

11.1.13.2 SPI 218

11.1.13.3 I2C 219

11.1.13.4 EUSART 220

11.1.14 Analog-to-Digital Converter 222

11.1.15 Analog Comparator 223

11.1.16 Special Features of the CPU 224

11.1.17 Instruction Set 225

11.1.18 Electrical Characteristics 225

11.2 ZiLOG Z8 Encore! XP F0830 Series 226

11.2.1 eZ8 CPU Description 227

11.2.2 The Z8 Encore! CPU Architecture 228

11.2.2.1 Fetch Unit 228

11.2.2.2 Execution Unit 228

11.2.3 Address Space 229

11.2.3.1 Register File 229

11.2.3.2 Program Memory 230

11.2.3.3 Data Memory 230

11.2.4 Peripherals Overview 231

11.2.5 Reset Controller and Stop Mode Recovery 233

11.2.6 Low-Power Modes 233

11.2.7 General-Purpose Input/Output 234

11.2.7.1 GPIO Architecture 234

11.2.7.2 GPIO Altemate Functions 235

11.2.7.3 GPIO Interrupts 235

11.2.8 Interrupt Controller 235

11.2.8.1 Master Interrupt Enable 236

11.2.8.2 Interrupt Vectors and Priority 236

11.2.9 Timers 237

11.2.9.1 ONE-SHOT Mode 237

11.2.9.2 CONTINUOUS Mode 238

11.2.9.3 COMPARATOR COUNTER Mode 238

11.2.9.4 PWM SINGLE OUTPUT Mode 238

11.2.9.5 PWM DUAL OUTPUT Mode 238

11.2.9.6 CAPTURE Mode 239

11.2.9.7 CAPTURE RESTART Mode 239

11.2.9.8 COMPARE Mode 239

11.2.9.9 GATED Mode 240

11.2.9.10 CAPTURE/COMPARE Mode 240

11.2.10 Watchdog Timer 240

11.2.11 Analog-to-Digital Converter 241

11.2.11.1 ADC Operation 242

11.2.11.2 ADC Timing 242

11.2.12 Comparator 243

11.2.13 Flash Memory 243

11.2.14 Nonvolatile Data Storage 243

11.2.15 On-Chip Debugger 244

11.2.16 Oscillator Control 245

11.2.16.1 Crystal Oscillator 245

11.2.16.2 Internal Precision Oscillator 246

11.2.17 eZ8 CPU Instructions and Programming 247

11.2.17.1 Program Stack 247

CHAPTER 12 16-BIT MICROCONTROLLER 250

12.0 16-bit Processor Overview 250

12.1 Freescale S12XD Processor Overview 250

12.1.1 XGATE Overview 253

12.1.1.1 XGATE Module 254

12.1.1.2 XGATE RISC Core 255

12.1.1.3 XGATE Programmer's Model 255

12.1.1.4 XGATE Memory Map 256

12.1.1.5 XGATE Semaphores 257

12.1.1.6 XGATE Modes of Operation 257

12.1.2 Clocking 257

12.1.2.1 Clock and Reset Generator(CRG) 258

12.1.2.2 Pierce Oscillator(XOSC) 258

12.1.3 Analog-to-Digital Convertor(ATD) 259

12.1.4 Enhanced Capture Timer(ECT) 261

12.1.4.1 Features 261

12.1.5 Pulse-Width Modulator(PWM) 262

12.1.5.1 Features 263

12.1.6 Interintegrated Circuit (IIC) 263

12.1.6.1 Features 263

12.1.7 Scalable Controller Area Network(CAN) 264

12.1.7.1 Features 264

12.1.7.2 CAN System 265

12.1.8 Serial Communication Interface(SCI) 265

12.1.8.1 Features 265

12.1.8.2 Functional Description 266

12.1.8.3 Data Formats 268

12.1.8.4 Receiver 268

12.1.8.5 Transmitter 268

12.1.8.6 Baud Rate Generator 268

12.1.9 Serial Peripheral Interface (SPI) 269

12.19.1 Features 269

12.19.2 Functional Description 271

12.1.10 Periodic Interrupt Timer (PIT) 272

12.1.10.1 Fealures 273

12.1.11 Voltage Regulator(VREG) 273

12.1.11.1 Features 274

12.1.12 Background Debug Module(BDM) 274

12.1.12.1 Features 274

12.1.13 Interrupt Module(XINT) 275

12.1.13.1 Features 275

12.1.13.2 Interrupt Nesting 276

12.1.14 Mapping Memory Control(MMC) 277

12.1.14.1 Features 277

12.1.15 Debug(DBG) 278

12.1.15.1 Features 278

12.1.16 External Bus Interface(XEBI) 280

12.1.16.1 Features 280

12.1.17 Port Integration Module(PIM) 280

12.1.17.1 Features 282

12.1.17.2 Port Pin 282

12.1.17.3 Functional Description 282

12.1.17.4 Data Register 282

12.1.17.5 Input Register 283

12.1.17.6 Data Direction Register 283

12.1.18.2 Kbyte EEPROM(EETX2K) 284

12.1.18.1 Features 284

12.1.18.2 Functional Description 285

12.1.18.3 EEPROM Module Security 286

12.1.19 512 Kbyte Flash Module(FTX512K4) 286

12.1.19.1 Features 286

12.1.20 Security(SEC) 286

12.1.20.1 Features 286

12.1.20.2 Modes of Operation 288

12.1.20.3 Secured Microcontroller 288

12.2 Texas Instruments MSP430TM Family 288

12.2.1 Low Power Design 291

12.2.2 Flexible Clock System 291

12.2.3 MSP430 CPU 292

12.2.4 Operating Modes 293

12.2.5 FLL+Clock Module 293

12.2.6 Flash Memory Controller 295

12.2.7 Hardware Multiplier 295

12.2.8 DMA Controller 296

12.2.9 Digital I/O 297

12.2.10 Watchdog Timer 297

12.2.11 Timers A and B 298

12.2.12 USART 299

12.2.13 USCI 301

12.2.13.1 UART Mode 301

12.2.13.2 SPI Mode 301

12.2.13.3 I2C Mode 303

12.2.14 ADC12 Function 304

12.2.15 DAC12 306

12.2.16 Embedded Emulation Module 306

12.2.16.1 Triggers 307

CHAPTER 13 INTELLECTUAL PROPERTY SoC CORES 309

13.0 SoC Overview 309

13.1 SoC Design Challenges 310

13.1.1 Configurable Processors 312

13.1.2 SoC Integration 314

13.1.3 Extensible Processors 316

13.1.4 Extensible Processors as RTL Alternatives 316

13.1.5 Explicit Control Scheme 317

13.2 The M1PS32 4K Processor Core Family 318

13.2.1 Key Features of the 4KE Family 319

13.2.2 Execution Unit 322

13.2.3 Multiply/Divide Unit(MDU) 323

13.2.4 Memory Manage Unit(MMU) 324

13.2.5 Cache Controller 325

13.2.6 Bus Interface Unit(BIU) 325

13.2.7 Power Management 326

13.2.8 Instruction Cache 326

13.2.9 Data Cache 327

13.2.10 EJTAG Controller 327

13.2.11 System Coprocessor 328

13.2.12 User-Defined Instructions(UDI) 329

13.2.13 Instruction Pipeline 329

13.2.13.1 Instruction Fetch 329

13.2.13.2 Execution 329

13.2.13.3 Memory Fetch 330

13.2.13.4 Align 330

13.2.13.5 Writeback 330

13.2.14 Instruction Cache Miss 330

13.2.15 Data Cache Miss 331

13.2.16 Multiply/Divide Operations 331

13.2.17 Branch Delay 332

13.2.18 Memory Management 332

13.2.18.1 MMU Overview 332

13.2.19 Modes of Operation 333

13.2.19.1 Virtual Memory Segments 333

13.2.19.2 Uset Mode 334

13.2.19.3 Kernel Mode 335

13.2.19.4 Debug Mode 335

13.3 Overview of the ARM 1022E Processor 336

13.3.1 Components of the Processor 337

13.3.1.1 Integer Unit 338

13.3.2 Registers 338

13.3.3 Integer Core 338

13.3.4 Integer Core Pipeline 339

13.3.4.1 Prefetch Unit 339

13.3.4.2 Load/Store Unit 342

13.3.5 Memory Management Unit 343

13.3.6 Caches and Write Buffer 343

13.3.7 Bus Interface 344

13.3.8 Topology 345

13.3.9 Coprocessor Interface 345

13.3.10 Coprocessor Pipeline 346

13.3.11 Debug Unit 346

13.3.12 Halt Mode 346

13.3.13 Monitor Debug-Mode 346

13.3.14 Clocking and PLL 347

13.3.15 ETM Interface Logic 348

13.3.16 Operating States 348

13.3.17 Switching State 350

13.3.18 Switching State During Exception Handling 350

13.3.19 Operating Modes 350

CHAPTER 14 TENSILICA CONFIGURABLE IP CORE 352

14.0 Introduction:Moore's Law Revisited 352

14.1 Chip Design Process 354

14.1.1 Building the Wrong Chip 354

14.1.2 Fundamental Trends of SoC Design 355

14.1.3 A New SoC for Every System is a Bad Idea 356

14.1.4 Nanometer Technology 357

14.1.5 SoC Design Reform 358

14.1.6 SoC Programmability 359

14.1.7 Programmability Versus Efficiency 360

14.1.8 The Key to SoC Design Success 363

14.1.9 An Improved Design Methodology for SoC Design 364

14.1.10 The Configurable Processor as a Building Block 365

14.1.11 Rapid SoC Development Using Automatically Generated Processors 366

14.1.12 The Starting Point:Essential Interfaces and Computation 367

14.1.13 Parallelizing a Task 367

14.1.14 Implications of Automatic Instruction-Set Generation 371

14.2 Tensilica Xtensa Architecture Overview 372

14.3 Principles of Instruction Set Design 374

14.4 Tensilica Xtensa Processor Uniqueness 374

14.5 Registers 375

14.6 Instruction Width 376

14.7 Compound Instructions 377

14.8 Branches 378

14.9 Instruction Pipeline 380

14.10 Limited Instruction Constant Width 381

14.11 Short Instruction Format 381

14.12 Register Windows 382

14.13 Xtensa LX2 Summary 383

CHAPTER 15 DIGITAL SIGNAL PROCESSORS 385

15.0 DSP Overview 385

15.1 TMS320C55x 385

15.1.1 Characteristics of the TMS320C55x 386

15.1.1.1 Market Segments 387

15.1.1.2 DSP Applications 387

15.1.2 Key Features of the C55x 387

15.1.3 Instruction Set Architecture 388

15.1.3.1 Instruction Pipelining 389

15.1.3.2 CPU Features 389

15.1.3.3 Instruction Set 390

15.1.4 Primary Functional Units 390

15.1.4.1 Instruction Buffer Unit 391

15.1.4.2 Program Flow Unit 393

15.1.4.3 Address Data Flow Unit 395

15.1.4.4 Data Computation Unit 396

15.1.5 Device Special Features 398

15.1.5.1 Low-Power Dissipation 398

15.1.6 Low-Power Design 398

15.1.6.1 Memory Accesses 398

15.1.6.2 Automatic Power Mechanisms 398

15.1.6.3 Low-Power Enhancements 399

15.1.6.4 Power Conservation 399

15.1.6.5 Idle Domains 399

15.1.6.6 Advanced Technology 399

15.1.7 Processor On-Chip Peripherals 400

15.1.7.1 On-Chip Memory 400

15.1.7.2 Analog-to-Digital Converter 400

15.1.7.3 DSP Clock Generator 401

15.1.7.4 DMA Controller 401

15.1.7.5 External Memory Interface 403

15.1.7.6 I2C Module 403

15.1.7.7 Multimedia/SD Card Controller 405

15.1.7.8 Programmable Timers 405

15.1.7.9 UART 405

15.1.7.10 USB Module 407

15.1.8 Emulation and Test 408

15.2 Analog Devices ADSP-BF535 Blackfin Processor 408

15.2.1 Portable Low-Power Architecture 409

15.2.2 System Integration 409

15.2.3 Processor Core 411

15.2.3.1 Instruction Pipeline 412

15.2.3.2 Instruction Pipeline Flow 412

15.2.4 Memory Architecture 413

15.2.4.1 Internal(On-Chip)Memory 414

15.2.4.2 PCI 415

15.2.4.3 I/O Memory Space 415

15.2.5 Event Handling 415

15.2.5.1 Core Event Controller(CEC) 416

15.2.5.2 System Interrupt Controller(SIC) 417

15.2.5.3 Interrupt Event Control 417

15.2.6 DMA Controller 418

15.2.7 External Memory Control 419

15.2.7.1 SDRAM Controller 420

15.2.8 Asynchronous Controller 420

15.2.9 PCI Interface 420

15.2.9.1 PCI Host Functions 420

15.2.9.2 PCI Target Function 421

15.2.10 USBDevice 421

15.2.11 Real-Time Clock 421

15.2.12 Watchdog Timer 422

15.2.13 Timers 422

15.2.14 Serial Ports 423

15.2.15 Serial Peripheral Interface(SPI)Ports 424

15.2.16 UART Ports 425

15.2.17 Dynamic Power Management 426

15.2.17.1 Full On Operating Mode 426

15.2.17.2 Active Operating Mode 426

15.2.17.3 Sleep Operating Mode 427

15.2.17.4 Deep Sleep Operating Mode 427

15.2.18 Operating Modes and States 427

INDEX 429