Digital logic: applications and design = 数字逻辑: 应用与设计 (英文版)PDF电子书下载

CHAPTER 1 Digital Concepts and Number Systems 1

Introduction 1

1.1 Digital and Analog：Basic Concepts 1

1.2 Some History of Digital Systems 4

1.3 Impact of Digital Technology on Society 6

1.4 Defining the Problem，an Introduction to Algorithms 7

1.5 Digital Systems Overview 9

1.6 Introduction to Number Systems 9

1.7 Positional Number Systems 10

1.7.1 Decimal Numbers 10

1.7.2 Binary Numbers 11

1.7.3 Octal Numbers 12

1.7.4 Hexadecimal Numbers 12

1.7.5 Counting in Base r 13

1.8 Number System Conversion 14

1.8.1 Binary to Hexadecimal Conversion 15

1.8.2 Hexadecimal and Octal to Binary Conversion 16

1.8.3 Binary to Decimal Conversion 16

1.8.4 Successive Division Radix Conversion 17

1.8.5 Fractional Radix Conversion，Successive Multiplication 18

1.8.6 Radix Conversion Algorithm 20

1.8.7 Decimal to Any Radix 21

1.8.8 Any Radix to Decimal 23

1.9 Binary Codes 23

1.9.1 Natural Binary Coded Decimal 23

1.9.2 Binary Codes （Weighted） 24

1.9.3 BCD Self-Complementing Codes 25

1.9.4 Unit Distance Code 26

1.9.5 Alphanumeric Codes 28

1.9.6 Signed Number Binary Codes 28

1.9.7 Signed Magnitude Codes 28

1.9.8 Complement Codes 29

1.10 Arithmetic 32

1.10.1 Binary Arithmetic 32

1.10.2 Binary Arithmetic Using Complement Codes 35

1.10.3 Hexadecimal Arithmetic 38

Summary 42

References 43

Glossary 44

Questions and Problems 45

CHAPTER 2 Boolean Switching Algebra 48

Introduction 48

2.1 Binary Logic Functions 48

2.1.1 IEEE Logic Symbols 54

2.1.2 Functions，Symbols，and Truth Tables 55

2.2 Switching Algebra 57

2.2.1 Equivalence 58

2.2.2 Closure 58

2.2.3 Identity 59

2.2.4 Associative Properties 59

2.2.5 Distributive Properties 61

2.2.6 Commutative Properties 62

2.2.7 Complement Property 62

2.2.8 Duality Property 62

2.2.9 Absorption Property 62

2.2.10 Idempotency Property 63

2.2.11 Binary Variables and Constants 63

2.2.12 DeMorgan’s Theorems 64

2.3 Functionally Complete Operation Sets 68

2.4 Reduction of Switching Equations Using Boolean Algebra 70

2.5 Realization of Switching Functions 73

2.5.1 Conversion of Switching Functions to Logic Diagrams 73

2.5.2 Converting Logic Diagrams to Switching Equations 77

Summary 80

References 80

Glossary 81

Questions and Problems 82

CHAPTER 3 Principles of Combinational Logic 84

Introduction 84

3.1 Definition of Combinational Logic 84

3.1.1 Problem Statements to Truth Tables 85

3.1.2 Deriving Switching Equations 89

3.2 Canonical Forms 91

3.3 Generation of Switching Equations from Truth Tables 93

3.4 Karnaugh Maps 96

3.4.1 Three- and Four-Variable Karnaugh Maps 97

3.4.2 Five- and Six-Variable Karnaugh Maps 107

3.4.3 Simplification Using Five-Variable Karnaugh Maps 109

3.4.4 Simplification Using Six-Variable Karnaugh Maps 112

3.4.5 Incompletely Specified Functions （Don’t Care Terms） 113

3.4.6 Simplifying Maxterm Equations 117

3.5 Quine-McClusky Minimization Technique 120

3.5.1 Quine-McClusky Using Don’t Care Terms 123

3.5.2 Reduced Prime Implicant Tables 125

3.6 Map-Entered Variables 129

3.7 Mixed Logic Combinational Circuits 135

3.7.1 Logic Symbols 136

3.7.2 Conversion to Bubble Logic 140

3.7.3 Synthesizing Switching Functions Using Bubble Notation 142

3.8 Multiple Output Functions 146

Summary 149

References 150

Glossary 150

Questions and Problems 151

CHAPTER 4 Analysis and Design of Combinational Logic 156

Introduction 156

4.1 General Approach to Combinational Logic Design 156

4.2 Introduction to Digital Integrated Circuits 164

4.3 Decoders 171

4.3.1 BCD Decoders 181

4.4 Encoders 185

4.5 Digital Multiplexers 190

4.5.1 Using Multiplexers as Boolean Function Generators 194

4.6 Adders and Subtractors 201

4.6.1 Cascading Full-Adders 205

4.6.2 Look-Ahead Carry 206

4.6.3 MSI Adders 207

4.6.4 Using MSI Adders as Subtractors 208

4.6.5 Using an MSI Adder as a BCD to Excess-3 Code Converter 211

4.6.6 BCD Adder 212

4.7 Binary Comparators 215

4.8 Arithmetic Logic Units 222

4.9 Array Multipliers 225

4.10 Tristate Buffers 228

4.11 Combinational Logic Hazards 231

4.11.1 Static Hazards 232

4.11.2 Dynamic Hazards 236

Summary 237

References 237

Glossary 238

Questions and Problems 239

CHAPTER 5 Flip-Flops，Simple Counters，and Registers 243

Introduction 243

5.1 Sequential Circuit Models 243

5.2 Flip-Flops 248

5.2.1 Flip-Flop Logic Symbols，Function，and Triggering 248

5.3 Flip-Flop Timing Specifications 265

5.3.1 Clock Parameters，Pulse Width，and Skew 265

5.3.2 Flip-Flop Timing，Setup，Hold，and Delay 267

5.3.3 Flip-Flop Metastability 268

5.4 Simple Counters 271

5.4.1 Divide by 2，4，and 8 Counters （Asynchronous） 272

5.4.2 Johnson Counter （Synchronous） 274

5.4.3 Ring Counter （Synchronous） 275

5.5 MSI Integrated Circuit Counters 276

5.5.1 MSI Asynchronous Counters 277

5.5.2 MSI Synchronous Counters 279

5.5.3 Control Signal Generation by Decoding Counter Outputs 283

5.5.4 A Counter Application：Digital Clock 287

5.5.5 IEEE Standard Symbols for MSI Counters 291

5.6 Registers 295

5.6.1 Registers Data Input and Output 295

5.6.2 Tristate Registers 300

5.6.3 Registers Connected to a Common Data Bus 305

5.6.4 Register Transfer Timing Considerations 310

Summary 312

References 313

Glossary 314

Questions and Problems 316

CHAPTER 6 Introduction to Sequential Circuits 322

Introduction 322

6.1 Mealy and Moore Models 322

6.2 State Machine Notation 323

6.2.1 Present State，Next State 324

6.2.2State Diagram 324

6.2.3State Table 328

6.2.4Transition Table 329

6.2.5Excitation Table and Equations 330

6.2.6Excitation Realization Cost 336

6.3Synchronous Sequential Circuit Analysis 339

6.3.1 Analysis Principles 340

6.3.2 Analysis Examples 340

6.4Construction of State Diagrams 348

6.4.1Up-Down Decade Counter 349

6.4.2Sequence Detectors 349

6.4.3Serial EX-3 to BCD Code Converter 354

6.5Counter Design 356

6.5.1 Modulo-8 Synchronous Counter 357

6.5.2 Up-Down Decade Counter Design 360

Summary 369

References 370

Glossary 370

Questions and Problems 371

CHAPTER 7 Sequential Circuit Design 375

Introduction 375

7.1 State Equivalence 375

7.2 State Reduction 376

7.2.1 Equivalence Classes 376

7.2.2 Implication Charts 378

7.3 State Reduction of Incompletely Specified State Tables 384

7.3.1 Merger Graphs 386

7.4 State Assignment Techniques 389

7.4.1 State Assignment Permutations 390

7.4.2 State Assignment Algorithm 392

7.4.3 Implication Graph 396

7.5 Algorithm State Machines 399

7.5.1 ASM Symbols 399

7.5.2 Elapsed Time Measurement，an ASM Design Example 404

7.6 Linked Sequential Machines 413

7.6.1 Computer Simulator and Graphic Plotter Interface，a Linked Sequential Machine Design Example 415

Summary 432

References 433

Glossary 433

Questions and Problems 434

CHAPTER 8 Asynchronous Sequential Circuits 441

Introduction to Asynchronous Sequential Machines 441

8.1 Fundamental and Pulse Mode Asynchronous Sequential Machines 442

8.2 Analysis of Asynchronous Sequential Machines 444

8.3 Deriving Flow Tables 452

8.4 State Assignment 456

8.4.1 Races and Cycles 456

8.4.2 Shared Row State Assignment 458

8.4.3 Multiple Row State Assignment 460

8.4.4 One Hot State Assignment 461

8.5 Asynchronous Design Problems 462

8.5.1 Asynchronous Design Problem 1 463

8.5.2 Asynchronous Design Problem 2 465

8.6 Data Synchronizers 470

8.6.1 Interface Protocol Asynchronous Cell 472

8.7 Mixed Operating Mode Asynchronous Circuits 474

Summary 477

References 478

Glossary 479

Questions and Problems 480

CHAPTER 9 Programmable Logic and Memory 485

Introduction 485

9.1 Memory 486

9.1.1 ROM，PROM，and EPROM 486

9.2 Using an EPROM to Realize a Sequential Circuit 491

9.3 Programmable Logic Devices 495

9.3.1 Programmable Logic Array （PLA） 496

9.3.2 Programmable Array Logic 498

9.3.3 Designing an Up-Down Decade Counter Using a PAL 502

9.3.4 Generic Array Logic 507

9.3.5 Designing a Synchronous Sequential Circuit Using a GAL 509

9.4 Erasable Programmable Logic Devices 514

9.4.1 Altera EP600 EPLD 517

9.4.2 Sequential Circuit Realization Using an EP600 519

9.5 PLD Computer-Aided Design 523

9.5.1 PLD Realization of Combinational Logic 525

9.5.2 Realizing Truth Tables Using a PLD Language 529

9.5.3 Realizing Flip-Flops Using a PLD Language 530

9.5.4 Realizing State Machines Using a PLD Language 530

9.6 Field Programmable Gate Arrays 534

9.6.1 Xilinx FPGA 535

9.6.2 System Development Tools for the Xilinx FPGA 542

9.6.3 Xilinx Macro Library 543

9.6.4 Actel FPGA 543

Summary 549

References 550

Glossary 551

Questions and Problems 552

CHAPTER 10 Digital Integrated Circuits 556

Introduction 556

10.1 Diodes as Switches 556

10.1.1 Diode Gates 558

10.2 Bipolar Transistor Switch 561

10.3 Diode Transistor Logic 562

10.4 Evolution from DTL to TTL 563

10.5 Transistor-Transistor Logic 565

10.5.1 TTL Circuit Operation 567

10.5.2 TTL Specifications 569

10.5.3 TTL Subfamilies 573

10.5.4 Schottky Junctions 578

10.5.5 Comparison of TTL Subfamily Specifications 579

10.5.6 Open Collector TTL Circuits 580

10.5.7 Tristate TTL Devices 584

10.5.8 Mixed TTL Subfamily Fan-Out 585

10.5.9 Other TTL Circuits 587

10.6 Emitter-Coupled Logic 590

10.6.1 Emitter-Coupled Logic Circuit 590

10.6.2 ECL Specifications 594

10.6.3 ECL to TTL and TTL to ECL Interfacing 595

10.7 Complementary Metal Oxide Semiconductor 597

10.7.1 Field Effect Transistors 597

10.7.2 MOSFETs 603

10.7.3 MOSFET Logic Gates 606

10.7.4 CMOS Logic Gates 609

10.7.5 Power Dissipation for High-Speed CMOS 612

10.7.6 Propagation Delay for High-Speed CMOS 613

10.7.7 CMOS Noise Margins 613

10.7.8 CMOS Subfamilies 613

Summary 615

References 615

Glossary 616

Questions and Problems 617

Appendix 1 TTL Analysis Spice Exercise 623

Appendix 2 Answers to Odd-Numbered Questions and Problems 627

Index 689