现代VLSI设计 基于IP核的设计 英文版PDF电子书下载

Chapter 1 Digital Systems and VLSI 1

1.1 Why Design Integrated Circuits? 3

1.2 Integrated Circuit Manufacturing 5

1.2.1 Technology 5

1.2.2 Economics 8

1.3 CMOS Technology 18

1.3.1 Power Consumption 18

1.3.2 Design and Testability 19

1.3.3 Reliability 20

1.4 Integrated Circuit Design Techniques 21

1.4.1 Hierarchical Design 22

1.4.2 Design Abstraction 25

1.4.3 Computer-Aided Design 31

1.5 IP-Based Design 33

1.5.1 Why IP? 33

1.5.2 Types of IP 34

1.5.3 IP Across the Design Hierarchy 35

1.5.4 The IP Life Cycle 37

1.5.5 Creating IP 37

1.5.6 Using IP 39

1.6 A Look into the Future 40

1.7 Summary 41

1.8 References 42

1.9 Problems 42

Chapter 2 Fabrication and Devices 43

2.1 Introduction 45

2.2 Fabrication Processes 45

2.2.1 Overview 46

2.2.2 Fabrication Steps 48

2.3 Transistors 52

2.3.1 Structure of the Transistor 52

2.3.2 A Simple Transistor Model 57

2.3.3 Transistor Parasitics 60

2.3.4 Tub Ties and Latchup 61

2.3.5 Advanced Transistor Characteristics 64

2.3.6 Leakage and Subthreshold Currents 70

2.3.7 Thermal Effects 72

2.3.8 Spice Models 72

2.4 Wires and Vias 73

2.4.1 Wire Parasitics 76

2.4.2 Skin Effect in Copper Interconnect 82

2.5 Fabrication Theory and Practice 84

2.5.1 Fabrication Errors 85

2.5.2 Scaling Theory and Practice 87

2.5.3 SCMOS Design Rules 90

2.5.4 Typical Process Parameters 95

2.5.5 Lithography for Nanometer Processes 95

2.5.6 3-D Integration 97

2.6 Reliability 98

2.6.1 Traditional Sources of Unreliability 99

2.6.2 Reliability in Nanometer Technologies 101

2.7 Layout Design and Tools 103

2.7.1 Layouts for Circuits 103

2.7.2 Stick Diagrams 106

2.7.3 Hierarchical Stick Diagrams 108

2.7.4 Layout Design and Analysis Tools 113

2.7.5 Automatic Layout 117

2.8 References 119

2.9 Problems 120

Chapter 3 Logic Gates 123

3.1 Introduction 125

3.2 Combinational Logic Functions 125

3.3 Static Complementary Gates 128

3.3.1 Gate Structures 128

3.3.2 Basic Gate Layouts 133

3.3.3 Logic Levels 137

3.3.4 Delay and Transition Time 140

3.3.5 Power Consumption 148

3.3.6 The Speed-Power Product 152

3.3.7 Layout and Parasitics 152

3.3.8 Driving Large Loads 156

3.4 Switch Logic 157

3.5 Alternative Gate Circuits 159

3.5.1 Pseudo-nMOS Logic 159

3.5.2 DCVS Logic 162

3.5.3 Domino Logic 163

3.6 Low-Power Gates 169

3.7 Delay through Resistive Interconnect 175

3.7.1 Delay through an RC Transmission Line 175

3.7.2 Delay through RC Trees 179

3.7.3 Buffer Insertion in RC Transmission Lines 182

3.7.4 Crosstalk between RC Wires 184

3.8 Delay through Inductive Interconnect 187

3.8.1 RLC Basics 187

3.8.2 RLC Transmission Line Delay 188

3.8.3 Buffer Insertion in RLC Transmission Lines 191

3.9 Design-for-Yield 193

3.10 Gates as IP 195

3.11 References 198

3.12 Problems 199

Chapter 4 Combinational Logic Networks 205

4.1 Introduction 207

4.2 Standard Cell-Based Layout 207

4.2.1 Single-Row Layout Design 208

4.2.2 Standard Cell Layout Design 217

4.3 Combinational Network Delay 219

4.3.1 Fanout 220

4.3.2 Path Delay 222

4.3.3 Transistor Sizing 226

4.3.4 Logic Synthesis 234

4.4 Logic and Interconnect Design 235

4.4.1 Delay Modeling 236

4.4.2 Wire Sizing 238

4.4.3 Buffer Insertion 238

4.4.4 Crosstalk Minimization 240

4.5 Power Optimization 246

4.5.1 Power Analysis 247

4.6 Switch Logic Networks 251

4.7 Combinational Logic Testing 255

4.7.1 Gate Testing 256

4.7.2 Combinational Network Testing 259

4.7.3 Testing and Yield 261

4.8 References 262

4.9 Problems 262

Chapter 5 Sequential Machines 267

5.1 Introduction 269

5.2 Latches and Flip-Flops 269

5.2.1 Timing Diagrams 269

5.2.2 Categories of Memory Elements 270

5.2.3 Latches 272

5.2.4 Flip-Flops 279

5.3 Sequential Systems and Clocking Disciplines 281

5.3.1 Clocking Disciplines 282

5.3.2 One-Phase Systems for Flip-Flops 283

5.3.3 Two-Phase Systems for Latches 284

5.4 Performance Analysis 292

5.4.1 Performance of Flip-Flop-Based Systems 293

5.4.2 Performance of Latch-Based Systems 297

5.4.3 Clock Skew 299

5.4.4 Retiming 308

5.4.5 Transient Errors and Reliability 309

5.5 Clock Generation 310

5.6 Sequential System Design 312

5.6.1 Structural Specification of Sequential Machines 312

5.6.2 State Transition Graphs and Tables 314

5.6.3 State Assignment 323

5.7 Power Optimization 329

5.8 Design Validation 330

5.9 Sequential Testing 332

5.10 References 340

5.11 Problems 340

Chapter 6 Subsystem Design 345

6.1 Introduction 347

6.2 Combinational Shifters 349

6.3 Adders 352

6.4 ALUs 360

6.5 Multipliers 360

6.6 High-Density Memory 369

6.6.1 ROM 372

6.6.2 Static RAM 372

6.6.3 The Three-Transistor Dynamic RAM 376

6.6.4 The One-Transistor Dynamic RAM 378

6.6.5 Flash Memory 380

6.7 Image Sensors 382

6.8 Field-Programmable Gate Arrays 385

6.9 Programmable Logic Arrays 387

6.10 Buses and Networks-on-Chips 391

6.10.1 Bus Circuits 391

6.10.2 Buses as Protocols 392

6.10.3 Protocols and Specifications 394

6.10.4 Logic Design for Buses 398

6.10.5 Microprocessor and System Buses 405

6.10.6 Networks-on-Chips 410

6.11 Data Paths 415

6.12 Subsystems as IP 417

6.13 References 422

6.14 Problems 422

Chapter 7 Floorplanning 425

7.1 Introduction 427

7.2 Floorplanning Methods 427

7.2.1 Chip-Level Physical Design 427

7.2.2 Block Placement and Channel Definition 431

7.2.3 Global Routing 436

7.2.4 Switchbox Routing 437

7.3 Global Interconnect 439

7.3.1 Interconnect Properties and Wiring Plans 439

7.3.2 Power Distribution 440

7.3.3 Clock Distribution 445

7.4 Floorplan Design 450

7.4.1 Floorplanning Tips 450

7.4.2 Design Validation 451

7.5 Off-Chip Connections 452

7.5.1 Packages 452

7.5.2 The I/O Architecture 457

7.5.3 Pad Design 458

7.6 References 461

7.7 Problems 462

Chapter 8 Architecture Design 471

8.1 Introduction 473

8.2 Hardware Description Languages 473

8.2.1 Modeling with Hardware Description Languages 474

8.2.2 VHDL 479

8.2.3 Verilog 487

8.2.4 C as a Hardware Description Language 494

8.3 Register-Transfer Design 495

8.3.1 Data Path-Controller Architectures 497

8.3.2 ASM Chart Design 500

8.4 Pipelining 509

8.5 High-Level Synthesis 518

8.5.1 Functional Modeling Programs 519

8.5.2 Data 520

8.5.3 Control 530

8.5.4 Data and Control 535

8.5.5 Design Methodology 538

8.6 Architectures for Low Power 539

8.6.1 Gate Power Control 540

8.6.2 Data Latching 541

8.6.3 Clock Gating 541

8.6.4 Architecture-Driven Voltage Scaling 541

8.6.5 Dynamic Voltage and Frequency Scaling 543

8.7 GALS Systems 544

8.8 Architecture Testing 545

8.9 IP Components 550

8.10 Design Methodologies 551

8.11 Multiprocessor System-on-Chip Design 559

8.12 References 565

8.13 Problems 565

Appendix A A Chip Designer's Lexicon 571

Appendix B Hardware Description Languages 589

B.1 Introduction 589

B.2 Verilog 589

B.2.1 Syntactic Elements 589

B.2.2 Data Types and Declarations 590

B.2.3 Operators 590

B.2.4 Statements 591

B.2.5 Modules and Program Units 592

B.2.6 Simulation Control 593

B.3 VHDL 594

B.3.1 Syntactic Elements 594

B.3.2 Data Types and Declarations 594

B.3.3 Operators 595

B.3.4 Sequential Statements 595

B.3.5 Structural Statements 597

B.3.6 Design Units 597

B.3.7 Processes 598

References 599

Index 613