数字集成电路 设计透视 英文 影印版PDF电子书下载

Chapter 1:Introduction 1

1.1 A Historical Perspective 2

1.2 Issues in Digital Integrated Circuit Design 4

1.3 To Probe Further 12

1.4 Exercises 15

PART Ⅰ:A CIRCUIT PERSPECTIVE 17

Chapter 2:The Devices 17

2.1 Introduction 18

2.2 The Diode 18

2.2.1 A First Glance at the Device 19

2.2.2 Static Behavior 22

2.2.3 Dynamic,or Transient,Behavior 27

2.2.4 The Actual Diode—Secondary Effects 36

2.2.5 The SPICE Diode Model 38

2.3 The MOS(FET)Transistor 39

2.3.1 A First Glance at the Device 39

2.3.2 Static Behavior 41

2.3.3 Dynamic Behavior 47

2.3.4 The Actual MOS Transistor—Secondary Effects 50

2.3.5 SPICE Models for the MOS Transistor 57

2.4 The Bipolar Transistor 62

2.4.1 A First Glance at the Device 63

2.4.2 Static Behavior 64

2.4.3 Dynamic Behavior 72

2.4.4 The Actual Bipolar Transistor—Secondary Effects 79

2.4.5 SPICE Models for the Bipolar Transistor 81

2.5 A Word on Process Variations 84

2.6 Perspective:Future Device Developments 86

2.7 Summary 87

2.8 To Probe Further 89

2.9 Exercises and Design Problems 90

Appendix A:Layout Design Rules 97

Appendix B:Small-Signal Models 105

Chapter 3:The Inverter 108

3.1 Introduction 109

3.2 Definitions and Properties 109

3.2.1 Area and Complexity 109

3.2.2 Functionality and Robostness:The Static Behavior 110

3.2.3 Performance:The Dynamic Behavior 116

3.2.4 Power and Energy Consumption 119

3.3 The Static CMOS Inverter 120

3.3.1 A First Glance 120

3.3.2 Evaluating the Robusmess of the CMOS Inverter:The Static Behavior 124

3.3.3 Performance of CMOS Inverter:The Dynamic Behavior 129

3.3.4 Power Consumption and Power-Delay Product 141

3.3.5 A Look into the Future:Effects of Technology Scaling 146

3.4 The Bipolar ECL Inverter 150

3.4.1 Issues in Bipolar Digital Design:A Case Study 150

3.4.2 The Emitter-Coupled Logic(ECL)Gate at a Glance 155

3.4.3 Robustness and Noise Immunity:The Steady-State Characteristics 160

3.4.4 ECL Switching Speed:The Transient Behavior 165

3.4.5 Power Consumption 176

3.4.6 Looking Ahead:Scaling the Technology 177

3.5 Perspective:Area,Performance,and Dissipation 179

3.6 Summary 179

3.7 To Probe Further 180

3.8 Exercises and Design Problems 181

Chapter 4:Designing Combinational Logic Gates in CMOS 189

4.1 Introduction 190

4.2 Static CMOS Design 191

4.2.1 Complementary CMOS 191

4.2.2 Ratioed Logic 202

4.2.3 Pass-Transistor Logic 210

4.3 Dynamic CMOS Design 222

4.3.1 Dynamic Logic:Basic Principles 223

4.3.2 Performance of Dynamic Logic 225

4.3.3 Noise Considerations in Dynamic Design 227

4.3.4 Cascading Dynamic Gates 231

4.4 Power Consumption in CMOS Gates 234

4.4.1 Switching Activity of a Logic Gate 234

4.4.2 Glitching in Static CMOS Circuits 240

4.4.3 Short-Circuit Currents in Static CMOS Circuits 242

4.4.4 Analyzing Power Consumption Using SPICE 244

4.4.5 Low-Power CMOS Design 246

4.5 Perspective:How to Choose a Logic Style 252

4.6 Summary 253

4.7 To Probe Further 254

4.8 Exercises and Design Problems 255

Appendix C:Layout Techniques for Complex Gates 264

Chapter 5:Very High Performance Digital Circuits 269

5.1 Introduction 270

5.2 Bipolar Gate Design 270

5.2.1 Logic Design in ECL 270

5.2.2 Differendal ECL 272

5.2.3 Current Mode Logic 278

5.2.4 ECL with Active Pull-Downs 281

5.2.5 Altemative Bipolar Logic Styles 283

5.3 The BiCMOS Approach 287

5.3.1 The BiCMOS Gate at a Glance 288

5.3.2 The Static Behavior and Robusmess Issues 291

5.3.3 Performance of the BiCMOS Inverter 293

5.3.4 Power Consumption 297

5.3.5 Technology Scaling 298

5.3.6 Designing BiCMOS Digital Gates 299

5.4 Digital Gallium Arsenide Design 300

5.4.1 GaAs Devices and Their Properties 301

5.4.2 GaAs Digital Circuit Design 307

5.5 Low-Temperature Digital Circuits 312

5.5.1 Low-Temperature Silicon Digital Circuits 312

5.5.2 Superconducting Logic Circuits 314

5.6 Perspective:When to Use High-Performance Technologies 321

5.7 Summary 322

5.8 To Probe Further 323

5.9 Exercises and Design Problems 325

Appendix D:The Schottky-Barrier Diode 330

Chapter 6:Designing Sequential Logic Circuits 332

6.1 Introduction 333

6.2 Static Sequential Circuits 333

6.2.1 Bistability 333

6.2.2 Flip-Flop Classification 335

6.2.3 Master-Slave and Edge-Triggered FFs 338

6.2.4 CMOS Static Flip-Flops 341

6.2.5 Bipolar Static Flip-Flops 345

6.3 Dynamic Sequential Circuits 347

6.3.1 The Pseudostatic Latch 348

6.3.2 The Dynamic Two-Phase Flip-Flop 350

6.3.3 The C2MOS Latch 351

6.3.4 NORA-CMOS—A Logic Style for Pipelined Structures 355

6.3.5 True Single-Phase Clocked Logic (TSPCL) 359

6.4 Non-Bistable Sequential Circuits 362

6.4.1 The Schmitt Trigger 363

6.4.2 Monostable Sequential Circuits 369

6.4.3 Astable Circuits 371

6.5 Perspective:Choosing a Clocking Strategy 374

6.6 Summary 375

6.7 To Probe Further 375

6.8 Exercises and Design Problems 376

PART Ⅱ:A SYSTEMS PERSPECTIVE 383

Chapter 7:Designing Arithmetic Building Blocks 383

7.1 Introduction 384

7.2 Datapaths in Digital Processor Architectures 384

7.3 The Adder 386

7.3.1 The Binary Adder:Definitions 386

7.3.2 The Full Adder:Circuit Design Considerations 389

7.3.3 The Binary Adder:Logic Design Considerations 396

7.4 The Multiplier 408

7.4.1 The Multiplier:Definitions 408

7.4.2 The Array Multiplier 408

7.4.3 Other Multiplier Structures 412

7.5 The Shifter 414

7.5.1 Barrel Shifter 414

7.5.2 Logarithmic Shifter 416

7.6 Other Arithmetic Operators 417

7.7 Power Considerations in Datapath Structures 418

7.7.1 Reducing the Supply Voltage 418

7.7.2 Reducing the Effective Capacitance 421

7.8 Perspective:Design as a Trade-off 424

7.9 Summary 425

7.10 To Probe Further 426

7.11 Exercises and Design Problems 427

Appendix E:From Datapath Schematics to Layout 434

Chapter 8:Coping with Interconnect 438

8.1 Introduction 439

8.2 Capacitive Parasitics 439

8.2.1 Modeling Interconnect Capacitance 439

8.2.2 Capacitance and Reliability—Cross Talk 445

8.2.3 Capacitance and Performance in CMOS 446

8.2.4 Capacitance and Performance in Bipolar Design 461

8.3 Resistive Parasitics 464

8.3.1 Modeling and Scaling of Interconnect Resistance 464

8.3.2 Resistance and Reliability—Ohmic Voltage Drop 467

8.3.3 Electromigration 469

8.3.4 Resistance and Performance—RC Delay 471

8.4 Inductive Parasitics 477

8.4.1 Sources of Parasitic Inductances 477

8.4.2 Inductance and Reliability—Voltage Drop 478

8.4.3 Inductance and Performance—Transmission Line Effects 482

8.5 Comments on Packaging Technology 493

8.5.1 Package Materials 494

8.5.2 Interconnect Levels 494

8.5.3 Thermal Considerations in Packaging 499

8.6 Perspective:When to Consider Interconnect Parasitics 500

8.7 Chapter Summary 501

8.8 To Probe Further 502

8.9 Exercises and Design Problems 503

Chapter 9:Timing Issues in Digital Circuits 510

9.1 Introduction 511

9.2 Clock Skew and Sequential Circuit Performance 511

9.2.1 Single-Phase Edge-Triggered Clocking 513

9.2.2 Two-Phase Master-Slave Clocking 515

9.2.3 Other Clocking Styles 517

9.2.4 How to Counter Clock Skew Problems 517

9.2.5 Case Study—The Digital Alpha 21164 Microprocessor 520

9.3 Self-Timed Circuit Design 522

9.3.1 Self-Timed Concept 522

9.3.2 Completion-Signal Generation 525

9.3.3 Self-Timed Signaling 528

9.4 Synchronizers and Arbiters 533

9.4.1 Synchronizers—Concept and Implementation 533

9.4.2 Arbiters 538

9.5 Clock Generation and Synchronization 538

9.5.1 Clock Generators 538

9.5.2 Synchronization at the System Level 540

9.6 Perspective:Synchronous versus Asynchronous Design 543

9.7 Summary 544

9.8 To Probe Further 544

9.9 Exercises and Design Problems 545

Chapter 10:Designing Memory and Array Structures 551

10.1 Introduction 552

10.2 Semiconductor Memories—An Introduction 552

10.2.1 Memory Classification 552

10.2.2 Memory Architectures and Building Blocks 555

10.3 The Memory Core 559

10.3.1 Read-Only Memories 559

10.3.2 Nonvolatile Read-Write Memories 573

10.3.3 Read-Write Memories(RAM) 578

10.4 Memory Peripheral Circuitry 590

10.4.1 The Address Decoders 591

10.4.2 Sense Amplifiers 596

10.4.3 Drivers/Buffers 603

10.4.4 Timing and Control 603

10.5 Memory Reliability and Yield 605

10.5.1 Signal-To-Noise Ratio 605

10.5.2 Memory yield 610

10.6 Case Studies in Memory Design 611

10.6.1 The Programmable Logic Array(PLA) 612

10.6.2 A 4 Mbit SRAM 616

10.7 Perspective:Semiconductor Memory Trends and Evolutions 617

10.8 Summary 620

10.9 To Probe Further 621

10.10 Exercises and Design Problems 622

Chapter 11:Design Methodologies 629

11.1 Introduction 630

11.2 Design Analysis and Simulation 630

11.2.1 Representing Digital Data as a Continuous Entity 631

11.2.2 Representing Data as a Discrete Entity 633

11.2.3 Using Higher-Level Data Models 637

11.3 Design Verification 638

11.3.1 Electrical Verification 639

11.3.2 Timing Verification 640

11.3.3 Functional(or Formal)Verification 641

11.4 Implementation Approaches 642

11.4.1 Custom Circuit Design 643

11.4.2 Cell-Based Design Methodology 646

11.4.3 Array-Based Implementation Approaches 655

11.5 Design Synthesis 667

11.5.1 Circuit Synthesis 668

11.5.2 Logic Synthesis 669

11.5.3 Architecture Synthesis 671

11.6 Validation and Testing of Manufactured Circuits 672

11.6.1 Test Procedure 674

11.6.2 Design for Testability 675

11.6.3 Test-Pattern Generation 684

11.7 Perspective and Summary 687

11.8 To Probe Further 688

11.9 Exercises and Design Problems 691

Problem Solutions 693

Index 700