Chapter 1 Concepts in Digital Systems 1
1．1 What Is a Digital System? 1
1．2 Views of a Digital System 2
1．2．1 Hierarchies 2
1．2．2 The Personal Computer 3
1．3 Introduction to Binary Numbers 4
1．4 Data Representations 6
1．5 Binary and Decimal Numbers 8
1．5．1 Binary-to-Decimal Conversion 8
1．5．2 Decimal-to-Binary Conversion 10
1．5．3 Fractions 12
1．5．4 Hexadecimal Numbers 14
1．6 Cells and Hierarchy 15
1．7 System Primitives 19
1．8 Metrics 22
1．9 Hierarchical Plan for the Book 23
1．10 Problems 26
Chapter 2 Boolean Algebra and Logic Gartes 29
2．1 Data Representation and Processing 29
2．2 Basic Logic Operations 31
2．2．1 The NOT Operation 31
2．2．2 The OR Gate 32
2．2．3 The AND Gate 33
2．3 Basic Identities 35
2．3．1 NOT Identity 35
2．3．2 OR Identities 35
2．3．3 AND Identities 36
2．4 Algebraic Laws 37
2．4．1 Commutative Laws 37
2．4．2 Associative Laws 37
2．4．3 Distributive Laws 38
2．5 NOR and NAND Gates 39
2．5．1 DeMorgan Theorems 41
2．6 Useful Boolean Identities 43
2．7Algebraic Reductions 44
2．8 Complete Logic Sets 47
2．8．1 NAND-Based Logic 48
2．8．2 NOR-Based Logic 48
2．9 IEEE Logic Gate Symbols 49
2．10 Problems 50
Chapter 3 Combinational Logic Design 57
3．1 Specifying the Problem 57
3．2 Canonical Logic Forms 59
3．2．1 Sum-of -Products（SOP） Form 59
3．2．2 Product-of-Sums（POS）Form 60
3．3 Extracting Canonical Forms 61
3．3．1 Minterms and Maxterms 63
3．3．2 Properties of SOP and POS Forms 65
3．4The Exclusive-OR and Equivalence Operations 66
3．5 Logic Arrays 68
3．5．1 AND and OR Arrays 69
3．5．2 SOP and POS Arrays 71
3．5．3 Application of Logic Arrays 75
3．6 BCD and 7-Segment Displays 76
3．7 Karnaugh Maps 80
3．7．1 2-Variable Karnaugh Maps 81
3．8 3-Variable Karnaugh Maps 84
3．8．1“Don t Care”Conditions 88
3．8．2 Alternative 3-Variable Map Layout 89
3．9 4-Variable Karnaugh Maps 89
3．10 The Role of the Logic Designer 93
3．11 Problems 94
Chapter 4 Digital Hardware 101
4．1 Voltages as Logic Variables 101
4．1．1 Logic Levels 103
4．2 Digital Integrated Circuits 104
4．2．1 Integration Levels 108
4．3 Logic Delay Times 109
4．3．1 Output Switching Times 110
4．3．2 The Propagation Delay 111
4．3．3 Fan-Out and Fan-In 112
4．3．4 Extension to Other Logic Gates 115
4．3．5 Logic Cascades 116
4．4 Basic Electric Circuits 119
4．4．1 Resistance 120
4．4．2 Capacitance 122
4．4．3 The RC Circuit 123
4．4．4 Application to Digital Circuits 128
4．5 Transmission Lines 128
4．5．1 Crosstalk 130
4．5．2 Electromagnetic Interference 131
4．6 Logic Families 132
4．6．2 TTL Integrated Circuits 133
4．6．1 CMOS 133
4．6．3 Emitter-Coupled Logic（ECL） 134
4．7 The Hardware Designer 135
4．8 Problems 135
Chapter 5 First Concepts in VHDL 143
5．1 Introduction 143
5．1．1 Basic Concepts 144
5．1．2 Using a Hardware Description Language 145
5．2 Defining Modules in VHDL 145
5．2．1 Concurrent Operations 152
5．2．2 Identifiers 155
5．2．3 Propagation Delay 156
5．3 Structural Modeling 158
5．4 Conditional Models 163
5．5 Binary Words 167
5．6 Libraries 169
5．7 Learning VHDL 171
5．8 Problems 172
Chapter 6 CMOS Logic Circuits 177
6．1 CMOS Electronics 177
6．2 Electronic Logic Gates 178
6．3 MOSFETs 179
6．4The NOT Function in CMOS 183
6．4．1 Complementary Pairs 185
6．4．2 The CMOS Inverter 186
6．5 Logic Formation Using MOSFETs 187
6．5．1 The NOR Gate 190
6．5．2 The NAND Gate 192
6．5．3 The CMOS-Logic Connection 193
6．6 Complex Logic Gates in CMOS 195
6．6．1 3-Input Logic Gates 196
6．6．2 A General 4-Input Gate 199
6．6．3 Logic Cascades 201
6．7 MOSFET Logic Formalism 202
6．7．1 FET Logic Descriptions 203
6．7．2 Voltage Transmission Characteristics 204
6．7．3 The Complementary Principle 206
6．7．4 Current Switching 208
6．7．5 Fiber-Optic Transmission Networks 210
6．8 Problems 212
Chapter 7 Silicon Chips and VLSI 219
7．1 What Is VISI Engineering? 219
7．1．1 Inside a Computer Chip 220
7．1．2 A Silicon Primer 220
7．1．3 The pn Junction 224
7．1．4 Silicon Devices 225
7．2 Lithography and Patterning 226
7．2．1 The Importance of Physical Layout 229
7．3 MOSFETs 230
7．3．1 MOSFET Switching 232
7．3．2 pFETs 237
7．3．3 MOSFET Design Rules 240
7．3．4 The Incredible Shrinking Transistor 241
7．4 Basic Circuit Layout 244
7．4．1 The CMOS Inverter 245
7．4．2 Electrical Modeling 246
7．5 MOSFET Arrays and AOI Gates 254
7．5．1 Wiring Strategies 254
7．5．2 NAND and NOR Layout 256
7．5．3 Complex Logic Gates 257
7．5．4 General Observations 258
7．6 Cells,Libraries,and Hierarchical Design 259
7．6．1 Creation of a Cell Library 260
7．6．2 Cell Placement 262
7．6．3 System Hierarchies 262
7．7 Floorplans and Interconnect Wiring 264
7．7．1 Interconnects 266
7．7．2 Wiring Delays 268
7．8 Problems 270
Chapter 8 Logic Components 275
8．1 Concept of a Digital Component 275
8．2 An Equality Detector 276
8．3 BCD Validity Detector 278
8．4 Line Decoders 280
8．5 Multiplexors 283
8．5．1 Multiplexors as Logic Elements 286
8．5．2 VHDL Description 288
8．6 Demultiplexors 289
8．6．1 VHDL Description 290
8．6．2 Multiplexed Transmission System 291
8．7 Binary Adders 292
8．7．1 The Full-Adder 293
8．7．3 Adder Cricuits 294
8．7．2 Half-Adders 294
8．7．4 VHDL Descriptions 296
8．7．5 Parallel Adders 298
8．7．6 CMOS Adder Circuits 300
8．8 Subtraction 301
8．8．1 Subtractor Logic Circuits 307
8．8．2 Negative Numbers 308
8．9 Multiplication 311
8．10 Transmission Gate Logic 314
8．10．1 Transmission Gate Multiplexors 315
8．10．2 TG XOR and XNOR Gates 317
8．10．3 CMOS Transmission Gates 318
8．11 Summary 319
8．12 Problems 320
Chapter 9 Memory Elements and Arrays 327
9．1 General Properties 327
9．2．1 The SR Latch 328
9．2 Latches 328
9．2．2 D Latch 331
9．3 Clocks and Synchronization 332
9．3．1 Clocked SR Latch 333
9．3．2 The D Latch 334
9．4 Master-Slave and Edge-Triggered Flip-Flops 334
9．4．1 A Master-Slave D-Type Flip-Flop 335
9．4．2 Other Types of Flip-Flops 341
9．5 Registers 343
9．5．1 Basic Storage Register 343
9．5．2 Shift Registers 344
9．6 Random-Access Memory（RAM） 348
9．6．1 Static RAM Cell 348
9．6．2 SRAM Array 350
9．6．3 Dynamic RAM 353
9．6．4 Parity and Error-Detection Codes 354
9．8 CD ROM 356
9．7 Read-Only Memory（ROM） 356
9．9 CMOS Memories 362
9．9．1 CMOS SRAMs 362
9．9．2 Dynamic RAM 363
9．9．3 ROMs 366
9．10 Transmission-Gate Circuits 367
9．10．1 Basic Latch 367
9．10．2 TG Flip-Flop 369
9．11 Problems 370
Chapter 10 Sequential Logic Networks 375
10．1 The Concept of a Sequential Network 375
10．1．1 Sequential Network Requirements 377
10．1．2 A General Sequential Network 379
10．2 Analysis of Sequential Networks 380
10．2．1 Single-State Variable Circuits 381
10．2．2 Multi-State Variable Networks 386
10．3 Sequential Network Design 389
10．2．3 General Characteristics 389
10．4 Binary Counters 391
10．5 The Importance of State Machines 397
10．6 Problems 397
Chapter 11 Computer Basics 403
11．1 An Overview of Computer Operations 403
11．1．1 Major Components of a Computer 404
11．1．2 What Can a Computer Do? 405
11．1．3 The von Neumann Model 405
11．1．4 Programming 407
11．1．5 Computer Registers 409
11．2 The Central Processor Unit:A First Look 409
11．2．1 The Instruction Fetch Network 410
11．2．2 Concept of the Datapath 412
11．2．3 Datapath Operations 413
11．3 Datapath Components 415
11．3．1 The Register File 416
11．3．2 The Arithmetic and Logic Unit 418
11．3．3 The Local Memory 423
11．4 Instructions and the Datapath 423
11．5 The Control Uint 431
11．6 CISC and RISC Architectures 435
11．6．1 CISC and Microprogramming 436
11．6．2 RISC Machines 437
11．6．3 Modern Computers 440
11．7 Floating-Point Operations 440
11．7．1 Arithmetic Operations 442
11．7．2 Application to Computers 443
11．8 VLSI Aspects of Computer Design 444
11．9 Problems 446
Chapter 12 Advanced Computer Concepts 451
12．1 Computing Speed 451
12．2 Pipelining 452
12．2．1 Data Hazards 457
12．2．2 Resolving Hazards 460
12．3Cache Memory 461
12．3．1 VLSI Aspects of Cache Memory 464
12．4 Superscalar Architectures 468
12．5 Basic Concepts of Parallel Computing 470
12．5．1 Classifications of Parallel Machines 473
12．5．2 Examples of Parallel Computations 475
12．5．3 General Architectures 479
12．5．4 General Design Variables 481
12．5．5 Interconnection Networks 482
12．5．6 The Challenge of Parallel Computing 484
12．5．7 Optical Interconnects 484
12．6 Problems 486
12．7 References 489
Epilog 491
Index 493